• Journal of Power Electronics
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• 제15권1호
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• pp.268-277
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• 2015

In this paper, a dual-converter three-phase pulse width modulation (PWM) rectifier based on unbalanced one-cycle control (OCC) strategy is proposed. The proposed rectifier is used to eliminate the second harmonic waves of DC voltage and distortion of line currents under unbalanced input grid voltage conditions. The dual-converter PWM rectifier employs two converters, which are called positive-sequence converter and negative-sequence converter. The unbalanced OCC system compensates feedback currents of positive-sequence converter via grid negative-sequence voltages, as well as compensates feedback currents of negative-sequence converter via grid positive-sequence voltages. The AC currents of positive- and negative-sequence converter are controlled to be symmetrical. Thus, the workload of every switching device of converter is balanced. Only one conventional PI controller is adopted to achieve invariant power control. Then, the parameter tuning is simplified, and the extraction for positive- and negative-sequence currents is not needed anymore. The effectiveness and the viability of the control strategy are demonstrated through detailed experimental verification.

• 전력전자학회논문지
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• 제20권1호
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• pp.19-30
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• 2015

A static synchronous compensator (STATCOM) applied to rapidly changing, highly unbalanced loads such as electric arc furnaces (EAFs), requires both positive-sequence and negative-sequence current control, which indicates fast response characteristics and can be controlled independently. Furthermore, a delta-connected STATCOM with cascaded H-bridge configuration accompanying multiple separate DC-sides, should have high performance zero-sequence current control to suppress a phase-to-phase imbalance in DC-side voltages when compensating for unbalanced load. In this paper, actual EAF data is analyzed to reflect on the design of current controllers and a pioneering zero-sequence current controller with a superb transient performance is devised, which generates an imaginary -axis component from the presumed response of forwarded reference. Via simulation and experiments, the performance of the positive, negative, and zero-sequence current control of a cascaded H-bridge STATCOM for EAF is verified.

• 한국통신학회논문지
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• 제13권5호
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• pp.422-428
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• 1988

반복 학습제어시스템은 시행을 반복함으로써 유한시간의 목표출력에 대하여 추종해 가도록 하는 것이다. 본 논문에서는 이산시간 시스템에 있어서의 이산 시간 학습제어 입력을 구하는 방법을 제안한다. 여기서 현재시행의 제어입력은 바로 전시행에서 입력 sequence와 time-shift된 error sequence의 선형조합에 의하여 구해진다. 컴퓨터로 제어되는 이산시간 시스템에서 error신호의 미분조작이 필요한 연속시간 Betterment Process에 비하여 error sequence의 time-shift조작은 보다 간단해지며 컴퓨터 시뮬레이션을 통하여 그 유효성을 확인하였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.463-467
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• 1992

This paper describes the automatic generation of sequence control programs for DCS(Distributed Control System), PLC(Programable Logic Controller) and so on. Since there is no same manufacturing process, it is difficult to standardize sequence programs. We propose the automatic sequence control program generator which is CAD software using knowledge engineering technique.

• 한국전기전자재료학회논문지
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• 제16권4호
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• pp.351-357
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• 2003

An easy learning elevator originated is opened to compare the existed teaming equipment, and it had a high studied efficiency that the sequence control circuit can open and close with the wire. The structure of equipment to be controlled from the first floor to the fifth floors is demostrated by the constructive apparatus with the lamps to express the function of the open-close of the door according to the cage moving with a mechanical actuation of the forward reverse breaker and the motor of load, and the mechanical actuation of hand-operation control components of push-button S/W and L/S and relay etc. These components let connect each other in order to control of the elevator function with the auto program and the designed sequence control circuit. Consequently the cage could go and come till 1∼5 steps with an auto program of the elevator and the sequence control circuit. The sequence control circuit is controlled by the step of forward and reverse to follow as that the sensor function of L/S1 ∼ L/S5 let posit with the control switchs of S/W1 ∼ S/W5 of PLC testing panel and switchs of S/W1 ∼ S/W5 installed on the transparent acryl plate of the frame. In here, improved apparatus is the hand-auto operation combined learning equipment to study the principle and technique of the originate sequence control circuit and the auto program of PLC.

• 한국산학기술학회논문지
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• 제11권1호
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• pp.107-112
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• 2010

PLC를 사용한 제어시스템에서 SFC 언어를 사용하면 전체 공정의 흐름을 이해하기 쉽고 유지보수가 용이하다. SFC 언어는 단일 시퀀스, 선택 시퀀스, 병렬 시퀀스로 나누어지고, 여러 조건에 맞게 처리하는 선택시퀀스로 프로그램 할 때 선택분기 스텝에 에러가 발생하면 전체 공정이 정지하게 된다. 이 에러스텝이 전체 공정에 크게 영향을 안주는 공정이라면 전체 공정을 정지시키지 않고 에러를 처리하면 손실은 줄어들게 된다. 본 논문에서는 선택시퀀스에서 리모트 콘트롤을 사용하여 선택시퀀스를 효율적으로 제어하는 방법을 제시하고 적용 예를 통해 그의 타당성을 확인하였다.

• 조명전기설비학회논문지
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• 제24권5호
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• pp.55-61
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• 2010

PLC 제어 시스템은 SFC 언어를 사용하여 설계할 경우, SFC 언어를 사용하면 제어의 흐름을 이해하기 쉽고, 유지보수가 용이하며 프로그램의 기술성이 뛰어나다. SFC 언어는 단일 시퀀스, 선택 시퀀스, 병렬 시퀀스로 나누어지며, 선택 시퀀스로 프로그래밍 하면 단일 시퀀스로 프로그램할 때보다 메모리의 크기가 커져야 한다. 본 논문에서는 선택 시퀀스의 기능을 단일 시퀀스로 구현하여 메모리의 크기를 줄여서 메모리의 효율을 향상시키는 방법을 제시하고, 실례를 통해 타당성을 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2319-2328
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• 2018

This paper introduces a control method for a transformerless MMC-HVDC system. The proposed method can effectively control the grid currents of the MMC-HVDC system under unbalanced grid conditions such as a single line-to-ground fault. The proposed method controls the currents of the positive sequence component and the negative sequence component without separating algorithms. Therefore, complicated calculations for extracting the positive sequence and the negative sequence component are not required. In addition, a control method to regulate a zero sequence component current under unbalanced grid conditions in the transformerless MMC-HVDC system is also proposed. The validity of the proposed method is verified through PSCAD/EMTDC simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.