• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.15-16
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• 한국소음진동공학회논문집
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• 제25권12호
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• pp.830-842
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• 2015

This paper aims to develop a SI(structural identification) technique using the kinetic energy optimization technique(KEOT) and the direct matrix updating method(DMUM) to decide on optimal location of sensors and to update FE model respectively, which ultimately contributes to a composition of more effective SHM. Owing to the characteristic structural flexing behavior of cable bridges, which makes them vulnerable to any vibration, systematic and continuous structural health monitoring (SHM) is pivotal for them. Since it is necessary to select optimal measurement locations with the fewest possible measurements and also to accurately assess the structural state of a bridge for the development of an effective SHM, a SI technique is as much important to accurately determine the modal parameters of the current structure based on the data optimally obtained. In this study, the KEOT was utilized to determine the optimal measurement locations, while the DMUM was utilized for FE model updating. As a result of experiment, the required number of measurement locations derived from KEOT based on the target mode was reduced by approximately 80 % compared to the initial number of measurement locations. Moreover, compared to the eigenvalue of the modal experiment, an improved FE model with a margin of error of less than 1 % was derived from DMUM. Finally, the SI technique for long-span bridges proposed in this study, which utilizes both KEOT and DMUM, is proven effective in minimizing the number of sensors while accurately determining the structural dynamic characteristics.

• 한국세라믹학회지
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• 제45권5호
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• pp.276-279
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• 2008

In this research, properties of $N_2$-doped $Sb_2Te_3$ thin film were evaluated using 4-point probe, XRD and AFM. $Sb_2Te_3$ material has faster crystallization rate than $Ge_2Sb_2Te_5$, but sheet resistance difference between amorphous and crystallization state is very low. This low sheet resistance difference decreases sensing margin in reading operation at PRAM device operation. Therefore, in order to overcome this weak point, $N_2$ gas was doped on $Sb_2Te_3$ thin film. Sheet resistance difference between amorphous and crystallized state of $N_2$-doped $Sb_2Te_3$ thin film showed about $10^4$ times higher than Un-doped $Sb_2Te_3$ thin film because of the grain boundary scattering.

• 한국정보통신학회논문지
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• 제16권7호
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• pp.1455-1462
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• 2012

본 논문에서는 BCD 공정 기반으로 PMIC용 고신뢰성 24비트 듀얼 포트(dual port) eFuse OTP 메모리를 설계하였다. 제안된 dynamic pseudo NMOS 로직회로를 이용한 프로그램 데이터 비교회로는 program-verify-read 모드에서 프로그램 데이터와 read 데이터를 비교하여 PFb(pass fail bar) 핀으로 비교 결과를 출력한다. 그래서 한 개의 PFb 핀만 테스트하므로 eFuse OTP 메모리가 정상적으로 프로그램 되었는지를 확인할 수 있다. 그리고 program-verify-read 모드를 이용하여 프로그램된 eFuse 저항의 변동을 고려한 가변 풀-업 부하(variable pull-up load)를 갖는 센싱 마진 테스트 회로를 설계하였다. Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 eFuse OTP 메모리의 레이아웃 면적은 $289.9{\mu}m{\times}163.65{\mu}m$($=0.0475mm^2$)이다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권6호
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• pp.297-301
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• 2006

In the present work, we investigate the characteristics of new composition material, chalcogenide $Ge_1Se_1Te_2$ material in order to overcome the problems of conventional PRAM devices. The Tc of $Ge_1Se_1Te_2$ bulk was measured $231.503^{\circ}C$ with DSC analysis. For static DC test mode, at low voltage, two different resistances are observed. depending on the crystalline state of the phase-change resistor. In the first sweep, the as-deposited amorphous $Ge_1Se_1Te_2$ showed very high resistance. However when it reached the threshold voltage(about 11.8 V), the electrical resistance of device was drastically reduced through the formation of an electrically conducting path. The phase transition between the low conductive amorphous state and the high conductive crystal]me state was caused by the set and reset pulses respectively which fed through electrical signal. Set pulse has 4.3 V. 200 ns. then sample resistance is $80\sim100{\Omega}$. Reset pulse has 8.6 V 80 ns, then the sample resistance is $50{\sim}100K{\Omega}$. For such high resistance ratio of $R_{reset}/R_{set}$, we can expect high sensing margin reading the recorded data. We have confirmed that phase change properties of $Ge_1Se_1Te_2$ materials are closely related with the structure through the experiment of self-heating layers.

• 한국전기전자재료학회논문지
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• 제20권7호
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• pp.575-580
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• 2007

A 16 Mb 1T1C FeRAM device was integrated with BLT capacitors. But a lot of cells were failed randomly during the measuring the bit-line signal distribution of each cell. The reason was revealed that the grain size and orientation of the BLT thin film were severely non-uniform. And the grain size and orientation were severely affected by the process conditions of post heat treatment, especially nucleation step. The optimized annealing temperature at the nucleation step was $560^{\circ}C$. The microstructure of the BLT thin film was also varied by the annealing time at the step. The longer process time showed the finer grain size. Therefore, the uniformity of the grain size and orientation could be improved by changing the process conditions of the nucleation step. The FeRAM device without random bit-fail cell was successfully fabricated with the optimized BLT capacitor and the sensing margin in bit-line signal distribution of it was about 340 mV.

• 한국정보전자통신기술학회논문지
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• 제15권4호
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• pp.249-256
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• 2022

드론 사진 측량의 경우 통상 상용 전문 SW인 Metashape, Pix4D Mapper, ContextCapture 및 간이 SW인 Global Mapper GIS의 "픽셀 to 포인트 도구" 모듈 등을 널리 사용하고 있다. 각 SW마다 고유의 항공 삼각측량법 해석에 대한 로직을 보유하고 있지만, 사용자가 SW를 선택하기 위해서는 지형공간정보의 좌표 값에 대한 비교 분석이 필요하다. 이를 위하여 드론 사진 측량을 위한 항공사진을 촬영하고, VRS-GPS 측량을 통하여 GCP 기준점 측량을 하여, 취득된 기초 데이터를 각 SW를 이용하여 데이터 처리를 한 후 정사 이미지과 DSM을 구축하고, GCP 기준점 측량 성과와 각 SW에서 취득된 정사 이미지 상의 GCP 대공표지의 중심점의 좌표(X,Y)및 DSM에 의한 GCP점의 높이 값(EL)을 비교했다. "공공측량 작업규정"에 따르면 각 SW의 결과치는 모두 오차범위 이내에 포함되어 어느 SW를 사용하더라도 규정에는 문제가 없는 것으로 판명되었다.

• 한국정보통신학회논문지
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• 제17권10호
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• pp.2359-2368
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• 2013

본 논문에서는 power IC에서 파워가 ON되어있는 동안 입력 신호인 RD(Read) 신호 포트에 glitch와 같은 신호 잡음이 발생하더라도 파워-업(power-up)시 readout된 DOUT 데이터를 유지하면서 다시 읽기 모드로 재진입하지 못하도록 막아주는 IRD(Internal Read Data) 회로를 제안하였다. 그리고 pulsed WL(Word-Line) 구동방식을 사용하여 differential paird eFuse OTP 셀의 read 트랜지스터에 수 십 ${\mu}A$의 DC 전류가 흐르는 것을 방지하여 blowing 안된 eFuse 링크가 EM(Electro-Migration)에 의해 blowing되는 것을 막아주어 신뢰성을 확보하였다. 또한 program-verify-read 모드에서 프로그램된 eFuse 저항의 변동을 고려하여 가변 풀-업 부하(variable pull-up load)를 갖는 센싱 마진 테스트 기능을 수행하는 동시에 프로그램 데이터와 read 데이터를 비교하여 PFb(pass fail bar) 핀으로 비교 결과를 출력하는 회로를 설계하였다. $0.18{\mu}m$ 공정을 이용하여 설계된 8-비트 eFuse OTP IP의 레이아웃 면적은 $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$이다.