• Proceedings of the KSRS Conference
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• v.1
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• pp.290-293
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• 2006

COMS (Communication, Ocean and Meteorological Satellite) shall be operated with two remote sensing payloads, MI (Meteorological Imager) and GOCI (Geostationary Ocean Color Imager). Since both payloads have rotating mechanisms, the dynamic coupling between two payloads is very important considering the pointing stability during GOCI operation. In addition, COMS adopts a single solar wing to improve the image quality, which leads to the unbalanced solar pressure torque in COMS. As a result, the off-loading of the wheel momentum needs to be performed regularly (2 times per day). Since the frequent off-loading could affect MI/GOCI imaging performance, another suboptimal off-loading time needs to be considered to meet the AOCS design requirements of COMS while having margin enough in the number of thruster actuations. In this paper, preliminary analysis results on the pointing stability and the wheel off-loading time selection with respect to MI/GOCI operations are presented.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.964-967
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• 2009

A new hybrid-type touch screen panel (TSP) has been developed based on a-Si:H TFT which can detect the change of both $C_{LC}$ and photo-current. This TSP can detect the difference of $C_{LC}$ between touch and no-touch states in unfavorable conditions such as dark ambient light and shadows. The hybrid TSP sensor consists of a detection area which includes one TFT for photo sensing and two TFTs for amplification. Compared to a single internal capacitive TSP or an optical sensing TSP, this new proposed hybrid-type TSP enables larger sensing margin due to embedding of both optical and capacitive sensors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.98-100
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• 2005

This paper describes link analysis on the processed data, HRIT (High Rate Information Transmission) and LRIT (Low Rate Information Transmission), for the preliminary design of interface between COMS (Communication, Ocean and Meteorological Satellite) and ground station. At the MODAC (MeteorologicaVOcean Data Application Center), the processed data are transmitted to user station via COMS with normalization and calibration by pre-processing of MI (Meteorological Imager) data. Due to consider satellite as radio relay, overall analysis containing uplink and downlink is needed. Specific link parameters can be obtained with using the outcomes of SRR (System Requirement Review) which was held on 13-14 June 2005, in Toulouse. From the relation between overall link margin and output power of HPA (High Power Amplifier) of MODAC, it is shown that even though the minimum power related with COMS receiving power range is transmitted at MODAC, the obtained link margin of HRIT could be above 3 dB at user station which antenna elevation angle is 10 degree.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Journal of Communications and Networks
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• v.18 no.5
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• pp.699-712
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• 2016

Recently, greedy algorithm has received much attention as a cost-effective means to reconstruct the sparse signals from compressed measurements. Much of previous work has focused on the investigation of a single candidate to identify the support (index set of nonzero elements) of the sparse signals. Well-known drawback of the greedy approach is that the chosen candidate is often not the optimal solution due to the myopic decision in each iteration. In this paper, we propose a tree search based sparse signal recovery algorithm referred to as the tree search matching pursuit (TSMP). Two key ingredients of the proposed TSMP algorithm to control the computational complexity are the pre-selection to put a restriction on columns of the sensing matrix to be investigated and the tree pruning to eliminate unpromising paths from the search tree. In numerical simulations of Internet of Things (IoT) environments, it is shown that TSMP outperforms conventional schemes by a large margin.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.303.1-303.1
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• 2014

좋은 전기적 특성을 가지면서 소자의 크기를 줄이기에 용이한 Gate-all-around (GAA) twin Si nanowire field-effect transistors (TSNWFETs)의 연구가 많이 진행되고 있다. Switching 특성과 단채널 효과가 없는 TSNWFETs의 특성은 GAA 구조의 본질적인 특성이다. TSNWFETs는 기존의 single Si nanowire TSNWFETs와 bulk FET에 비하여 Drive current가 nanowire의 지름에 많은 영향을 받지 않는다. 그러나 TSNWFETs의 전체 on-current는 훨씬 작고 nanowire의 지름이 작아지면서 줄어들게 되면서 소자의 sensing speed와 sensing margin 특성의 악화를 가지고 온다. GAA TSNWFETs의 제작 및 전기적 실험에 대한 연구는 많이 진행되었으나, GAA TSNWFETs의 전기적 특성에 대한 이론적 연구는 매우 적다. 본 연구에서는 GAA TSNWFETs의 nanowire 크기에 따른 전기적 특성을 관찰하였다. GAA TSNWFETs와 bulk FET의 전기적 특성을 양자역학을 고려하여 3차원 TCAD 시뮬레이션을 툴을 이용하여 계산하였다. GAA TSNWFETs와 bulk FET의 전류-전압 특성 계산을 통해 on-current 크기, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage를 보았다. 전류가 흐르는 경로와 전기적 특성의 물리적 의미에 대한 연구를 위해 TSNWFETs에서의 전류 밀도, conduction band edge, potential 특성을 분석하였다. 시뮬레이션 결과를 통해 Switching 특성, 단채널 효과에 대한 면역 특성, nanowire의 단면적에 따른 전류 흐름을 보았다. nanowire의 크기가 작아지면서 DIBL이 증가하고 문턱전압과 전체 on-current는 감소하면서 소자의 특성이 악화된다. 이러한 결과는 GAA TSNWFETs의 전기적 특성을 이해하고 좋은 소자 특성을 위한 구조를 연구하는데 많은 도움이 될 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).