• Transactions on Electrical and Electronic Materials
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• 제15권4호
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• pp.221-225
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• 2014

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.1-4
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• 2006

Recently, Ball Grid Arrays(BGAs) are getting used more frequently for a package type. The connectors on a BGA consist of a large number of small solder balls in a grid shape on its bottom side. However, since balls of BGAs mounted on PCBs are not visible, inspection before mounting them is indispensable. High speed non-contact 3D measurement technologies are necessary far real-time measurement of ball height, the most important inspection item. In this paper, an accurate 3D data acquisition system for BGAs is proposed that can acquire 3D profile at high speed using a 3D smart camera and laser slit ray projection. Some clipping and morphological filtering operations are employed to remove spiky error data, which occur due to reflections from some ball area to camera direction.

• 반도체디스플레이기술학회지
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• 제4권4호
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• pp.27-31
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• 2005

This article contains the development of FPC bonder that used for repair or trial product. Nowadays, in FPO module process (including PDP) accept the thermo-compress bonding method when attach FPC(Flexible Printed Circuit Board), TCP(Tape Carrier Package) and COF(Chip on the FPC) by ACF(Anisotropic Conductive Film). This system consists of ACF attachment part, pre-bonding part, main bonding part, loading / unloading part. This composition is a stand-alone system, not an in-line system. Hereafter, this composition should be developing into in-line system in all area of FPD industry.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2013년도 자성 및 자성재료 국제학술대회
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• pp.32-32
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• 2013

Using the Vienna ab initio simulation package (VASP) incorporating van der Waals interaction, we have explored structural, adsorption, and magnetic properties of Ni(111)/BN/Co(111) systems. We have found that both Ni(111) and Co(111) layers shows half metallic state, while the spacer BN layer becomes weak metal for one monolayer (ML) thickness and an insulating barrier for two ML thickness. The half metallic states in both Ni(111) and Co(111) layers are robust because it is unchanged independently on the magnetic coupling of Ni(111) and Co(111). This finding suggests that the Ni(111)/BN/Co(111) systems can be utilized for perfect tunneling magnetoresistance system. Moreover, it can be applied for potential spin injecting into semiconductor in FM/semiconductor system due to the fact that the half metallic state in FM layers at the interface will be unchanged.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 반도체디스플레이기술학회지
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• 제10권1호
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• pp.17-22
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• 2011

LEDs(Light Emitting Diodes) are becoming widely used and increasingly in demand. Quality inspection of the LEDs has become more important. Two-dimensional inspection systems are limited in inspection capability, so threedimensional(3-D) inspection systems are needed. In this paper, a cost-effective and simple 3-D measurement system of LED packages using phase measuring profilometry(PMP) is proposed. The proposed system uses a pico projector to project sinusoidal fringe patterns and to shift phases instead of piezocrystal. It was evaluated using extremely accurate gauge blocks, yielding excellent repeatability of about 12 um(3-sigma). 3-D measurements of various LED packages were performed to demonstrate the applicability and efficiency of the proposed system.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 반도체디스플레이기술학회지
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• 제20권3호
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• pp.103-107
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• 2021

In this paper, a capacitive water level sensor for boilers was developed. In order to accurately monitor the water level in a high-temperature boiler that generates a lot of precipitates, the occurrence of precipitates on the surface of the water level sensor should be small, and a sensor capable of measuring even if the sensor surface is somewhat contaminated is required. The capacitive water level sensor has a structure in which one of the two electrodes is insulated with Teflon coating, and the stainless steel package of the water level sensor is brought into contact with the water tank so that the entire water tank becomes another electrode of the water level sensor. A C-V converter that converts the capacitance change of the capacitive water level sensor into a voltage change was developed and integrated with the water level sensor to minimize noise. The performance of the developed capacitive water level sensor was evaluated through measurement.