• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.219-229
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• 2012

In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.3
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• pp.474-478
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• 2018

The use of metals such as aluminum and titanium and the related industrial facilities have been continuously increasing to meet the requirements of the improvement of high-tech products due to the development of industry, and explosion of metal dust. Semiconductor process Metal dust is essential, but research is insufficient. The purpose of this study is to identify risk by analyzing the quantitative risk such as maximum explosion pressure and minimum explosion concentration applied international test standard in order to select the semiconductor process facilities handling dust and to predict possible risk of accidents.

• Korean Management Science Review
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• v.18 no.1
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• pp.1-13
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• 2001

Despite that the semiconductor industry plays an important role to our economy, it has abnormal industrial structure stressing too much on memory chips. Thus, it is essential for our corporate to develop nonmemory chips to obtain technological leadership in a highly competitive semiconductor market. In this study, we demonstrate how benefit/cost analysis using the Analytic Hierarchy process (AHP) can be used for the proper selection of nonmemory semiconductor chips: Microprocessor, ASIC, digital IC and Analogue IC. The final results show that ASIC is the most attractive chip to develop, followed by Analogue IC, digital IC and Microprocessor. This is Somewhat consistent with the information that we found with respect to the elements that were taken into consideration. Sensitivity analysis is also provided here.

• Journal of the Korea Society for Simulation
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• v.14 no.4
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• pp.55-68
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• 2005

The advancement in semiconductor technology is leading toward smaller critical dimension designs and larger wafer manufactures. Due to such phenomena, semiconductor industry is in need of an accurate control of the process. Photolithography is one of the key processes where the pattern of each layer is formed. In this process, precise superposition of the current layer to the previous layer is critical. Therefore overlay parameters of the semiconductor photolithography process is targeted for this research. The complex relationship among the input parameters and the output metrologies is difficult to understand and harder yet to model. Because of the superiority in modeling multi-nonlinear relationships, neural networks is used for the simulator modeling. For training the neural networks, conjugate gradient method is employed. An experiment is performed to evaluate the performance among the proposed neural network simulator, stepwise regression model, and the currently practiced prediction model from the test site.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.34-37
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• 2004

Recently advancing mobile communication tools and I.T industry, semiconductor device is requested more integrated, faster operation time and more scaled-down. Because of these reasons semiconductor device is requested multilayer interconnection. For the multilayer interconnection chemical mechanical polishing (CMP) becomes one of the most useful process in semiconductor manufacturing process. In this experiment, we focus on understand the characterize and improve the CMP technology by control of slurry flow rate. Consequently, we obtain that optimal flow rate of slurry is 170ml/min, since optimal conditions are less chemical flow and performance high with good selectivity to Ta. If we apply this results to copper CMP process. it is thought that we will be able to obtain better yield.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.12
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• pp.1072-1080
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• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• Vacuum Magazine
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• v.1 no.3
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• pp.21-27
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• 2014

Advanced process and integration for future semiconductor devices is approaching the physical limit. The new materials with low dimensional structure have recently attracted great attention due to its expandability for the future electronic devices. In order to apply the materials to future semiconductor devices, the control of carrier scattering is critical issue. That is, the carrier scattering with physical quantity in low dimensional structure significantly modulates the device characteristics. We introduce the role of defect in several future semiconductor materials and devices. The analysis of defect in the structure becomes the most important techniques. In particular, surface defect in nano structures totally controls the device characteristics. The changes imply that the metrology field is leading the future industry for semiconductor.

• The Magazine of the IEIE
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• v.34 no.7 s.278
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• pp.54-66
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• 2007

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.191-193
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• 2002

• Proceedings of the Korean Ceranic Society Conference
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• 2003.10a
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• pp.21.2-21
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• 2003