• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.1-9
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• 2002

The distribution characteristics of data retention time for DRAM was studied in connection with the probability distribution of the cell parameters. Using the cell parameters and the transient characteristics of cell node voltage, data retention time was investigated. The activation energy for dielectric layer growth on cell capacitance, the recombination trap energy for leakage current in the junction depletion region, and the sensitivity characteristics of sense amplifier were used as the random variables to perform the Monte Carlo simulation, and the probability distributions of cell parameters and distribution characteristics of cumulative failure bit on data retention time in DRAM cells were calculated. we found that the sensitivity characteristics of sense amplifier strongly affected on the tail bit distribution of data retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• The Korean Journal of Applied Statistics
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• v.35 no.3
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• pp.407-419
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• 2022

The semiconductor fabrication process is complex and time-consuming. There are sometimes errors in the process, which results in defective die on the wafer bin map (WBM). We can detect the faulty WBM by finding some patterns caused by dies. When one manually seeks the failure on WBM, it takes a long time due to the enormous number of WBMs. We suggest a two-step approach to discover the probable pattern on the WBMs in this paper. The first step is to separate the normal WBMs from the defective WBMs. We adapt a hierarchical clustering for de-noising, which nicely performs this work by wisely tuning the number of minimum points and the cutting height. Once declared as a faulty WBM, then it moves to the next step. In the second step, we classify the patterns among the defective WBMs. For this purpose, we extract features from the WBM. Then machine learning algorithm classifies the pattern. We use a real WBM data set (WM-811K) released by Taiwan semiconductor manufacturing company.

• Journal of Technology Innovation
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• v.26 no.3
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• pp.37-68
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• 2018

Since the 20th century, automobiles, which are the most common means of transportation, have been evolving as the use of electronic control devices and automotive semiconductors increases dramatically. Automotive semiconductors are a key component in automotive electronic control devices and are used to provide stability, efficiency of fuel use, and stability of operation to consumers. For example, automotive semiconductors include engines control, technologies for managing electric motors, transmission control units, hybrid vehicle control, start/stop systems, electronic motor control, automotive radar and LIDAR, smart head lamps, head-up displays, lane keeping systems. As such, semiconductors are being applied to almost all electronic control devices that make up an automobile, and they are creating more effects than simply combining mechanical devices. Since automotive semiconductors have a high data rate basically, a microprocessor unit is being used instead of a micro control unit. For example, semiconductors based on ARM processors are being used in telematics, audio/video multi-medias and navigation. Automotive semiconductors require characteristics such as high reliability, durability and long-term supply, considering the period of use of the automobile for more than 10 years. The reliability of automotive semiconductors is directly linked to the safety of automobiles. The semiconductor industry uses JEDEC and AEC standards to evaluate the reliability of automotive semiconductors. In addition, the life expectancy of the product is estimated at the early stage of development and at the early stage of mass production by using the reliability test method and results that are presented as standard in the automobile industry. However, there are limitations in predicting the failure rate caused by various parameters such as customer's various conditions of use and usage time. To overcome these limitations, much research has been done in academia and industry. Among them, researches using data mining techniques have been carried out in many semiconductor fields, but application and research on automotive semiconductors have not yet been studied. In this regard, this study investigates the relationship between data generated during semiconductor assembly and package test process by using data mining technique, and uses data mining technique suitable for predicting potential failure rate using customer bad data.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.43-47
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• 2004

We have been using Moisture Barrier Bags for dry packing of semiconductor packages to prevent moisture from absorbing during shipping. Moisture barrier bag material is required to be waterproof, vapor proof and offer superior ESD (Electro-static discharge) and EMI shielding. Also, the bag should be formed easily to the shape of products for vacuum packing while providing excellent puncture resistance and offer very low gas ＆ moisture permeation. There are some problems like pinholes and punctured bags after sealing and before the surface mount process. This failure may easily result in package pop corn crack during board mounting. The bags should be developed to meet the requirements of excellent electrical and physical properties by means of optimization of their raw material composition and their thickness. This study investigates the performance of moisture barrier bags by characterization of their mechanical endurance, tensile strength and through thermal analysis. By this study, we arrived at a robust material composition (polyester/Aluminate) for better packing.

• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.5-8
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• 2003

In this study, as Cu diffusion barrier, tantalum nitrides were successfully deposited on Si(100) substrate and $SiO_2$ by plasma assisted atomic layer deposition(PAALD) and thermal ALD, using pentakis (ethylmethlyamino) tantalum (PEMAT) and NH$_3$ as precursors. The TaN films were deposited at $250^{\circ}C$ by both method. The growth rates of TaN films were 0.8${\AA}$/cycle for PAALD and 0.75${\AA}$/cycle for thermal ALD. TaN films by PAALD showed good surface morphology and excellent step coverage for the trench with an aspect ratio of h/w -1.8:0.12 mm but TaN films by thermal ALD showed bad step coverage for the same trench. The density for PAALD TaN was 11g/cmand one for thermal ALD TaN was 8.3g/$cm^3$. TaN films had 3 atomic % carbon impurity and 4 atomic % oxygen impurity for PAALD and 12 atomic % carbon impurity and 9 atomic % oxygen impurity for thermal ALD. The barrier failure for Cu(200 nm)/TaN(10 nm)/$SiO_2$(85 nm)/ Si structure was shown at temperature above $700^{\circ}C$ by XRD, Cu etch pit analysis.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.14-19
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• 2002

In this study, as Cu diffusion barrier, tantalum nitrides were successfully deposited on Si(100) substrate and SiO2 by plasma assisted atomic layer deposition(PAALD) and thermal ALD, using pentakis (ethylmethlyamino) tantalum (PEMAT) and $NH_3$ as precursors. The TaN films were deposited on $250^{\circ}$C by both method. The growth rates of TaN films were $0.8{\AA}$/cycle for PAALD and $0.75{\AA}$/cycle for thermal ALD. TaN films by PAALD showed good surface morphology and excellent step coverage for the trench with an aspect ratio of h/w - $1.8 : 0.12 \mu\textrm{m}$ but TaN films by thermal ALD showed bad step coverage for the same trench. The density for PAALD TaN was $11g/\textrm{cm}^3$ and one for thermal ALD TaN was $8.3g/\textrm{cm}^3$. TaN films had 3 atomic % carbon impurity and 4 atomic % oxygen impurity for PAALD and 12 atomic % carbon impurity and 9 atomic % oxygen impurity for thermal ALD. The barrier failure for Cu(200nm)/TaN(l0nm)/$SiO_2(85nm)$/Si structure was shown at temperature above $700^{\circ}$C by XRD, Cu etch pit analysis.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.123-128
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• 2021

Liquid dispensing systems are extensively used in various industries such as display, semiconductor, and battery manufacturing. Of the many types of dispensers, drop-on-demand piezoelectric jetting systems are widely used in semiconductor industries because of their ability to dispense minute volumes with high precision. However, due to the problems of nozzle clogging and undesirable dispensing behavior in these dispensers, which often result in device failure, the use of highly viscous fluids is limited. Accordingly, we studied the behaviors of droplet formation based on changes in viscosity. The effects of surface energy and the inner diameters of needle-type nozzles were also studied. Results showed that nozzles with lower surface energies reduced the ejection volume of droplets when a smaller nozzle diameter (0.21 mm in this study) was applied. These results indicate that the hydrophobic treatment of nozzle surfaces and the use of smaller nozzle diameters are critical factors enabling the use of highly viscous fluids in precision dispensing applications.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.121-126
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• 2017

EES System support to maximize equipment efficiency by providing real-time information of main equipment which has a significant effect on product quality and productivity, and to prevent equipment failure by detecting equipment abnormality in advance. Smart Equipment Engineering System(S-EES) integrates the activities performed at equipment that are the core of production activities and manages them by system so as to maximize the efficiency of equipment and raise the quality level of products to one level. In other words, when the product is put into the equipment, the recipe is downloaded through the RMS, the recipe is set to the optimal condition through R2R(process control), and the system detects and controls the abnormality of the equipment during operation through the FDC function in real time it means. In this way, we are working with the suitable recipe that matches the lot of product, detecting the abnormality of the equipment during operation, preventing the product from being defective, and establishing a system to maximize the efficiency through real-time equipment management. In this study, we review the present status and problems of equipment management in actual production lines, collect the requirements of the manufacturing line for the PCB line, design and develop the system, The measurement model was studied.