• Journal of the Korean Society for Precision Engineering
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• v.14 no.12
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• pp.48-55
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• 1997

A useful method to detect tool breakage suing neural network of cutting force signal is porposed and implemented in a basic cutting process. Cutting signal is gathered by tool dynamometer and normalized as a preprocessing. The cutting force signal level is continually monitored and compared with the predefined level. The neural network has been trained normalized sample data of the normal operation and cata-strophic tool failure using backpropagation learning process. The develop[ed system is verified to be very effective in real-time usage with minor modification in conventional cutting processes.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.4
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• pp.106-113
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• 2000

One of the recent changes in machining technology is rapid application of micro- and high precision grinding processes. A fine groove generation is necessary for the fabrication of optics, electronics and semiconductor parts. Slot grinding is very efficient for the generation of micro ordered groove with hard and brittle materials. In the process of slot grinding, chipping at the sharp edges and microcracks of the ground grooves are inevitable defects. Chipping should be reduced for the improvement of surface integrity. Mechanical contact with diamond grits causes microcracks at the grooves. This damage resides subsurface, and can be the cause of failure of the punch die. This paper deals with chipping generation at the sharp edges, surface integrity of side groove and fracture strength is related to the microcracks in the slot grinding.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.77-82
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• 1996

The breakdown characteristics of metal-oxide-semiconductor(MOS) capacitors fabricated by Al, polysilicon, and tungsten polycide gate electrodes onto gate oxide was evaluated by time zero dielectric breakdwon (TZDB). The average breakdown field of the gate oxide with tungsten polycide electride was lower than that of the polysilicon electrode. The B model (1~8MV/cm) failure of the gate oxide with tungsten polycide electrode was increased with increasing annealing temperature in the dry $O_{2}$ ambient. This is attributed ot fluorine and tungsten diffusion from thungsten silicide film into the gate oxide, and stress increase of tungsten polcide after annealing treatment.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.33-39
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• 2014

To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

• Journal of the Korean Ceramic Society
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• v.54 no.1
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• pp.66-69
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• 2017

In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.224-225
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• 2000

Transparent and hard materials such as sapphire are used for many industrial applications as optical windows, hard materials on mechanical contact against abrasion, and substrate materials for opto-electronic semiconductor devices such as blue LED and blue LD etc. The materials should be cut along the proper shapes possible to be used for each application. In case of blue LED, the blue LED wafer should be cut to thousands of blue LED pieces at the final stage of the manufacturing process. The process of cutting the wafer is usually divided into two steps. The wafer is scribed along the proper shapes in the first step. It is inserted between transparent flexible sheets for easy handling. And then, it is broken and split in the next step. Harder materials such as diamonds are usually used to scribe the wafer, while it has a problem of low depth of scribing and abrasion of the harder material itself. The low depth of scribing can induce failure in breaking the wafer along the scribed line. It was also known that the expensive diamond tip should be replaced frequently for the abrasion. (omitted)

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.122-131
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• 2003

In this study, some characteristics of conductive and non-conductive adhesive inter-connections are derived, based on data from literature and own projects. Assembly of flip chip on flex is taken as a carrier. Potential failure mechanisms of adhesive interconnections reported in literature are reviewed. Some methods that can be used to evaluate the quality of adhesive interconnections and to evaluate their aging behavior are given. Possible finite element simulation approaches are introduced and the required critical materials properties are summarized. Response to temperature and moisture, resistance to reflow soldering and resistance to rapid change in temperature and humidity are elaborated. The effect of post cure during accelerated testing is discussed. This study shows that only a combined approach using finite element simulations, and use of appropriate experimental evaluation methods can result in revealing, understanding and quantifying the complex degradation mechanisms of adhesive interconnections during aging.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.3
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• pp.224-230
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• 2009

FIB has been commonly used as a very powerful tool in the semiconductor industry. It is mainly used for mask repair, device correction, failure analysis and IC error correction, etc. Currently, FIB is not being applied to the fabrication of the micro and nano-structured mold, because of low productivity. And also sputtering rate has been required to fabricate 3D shape. In the paper, we studied the FIB-Sputtering rate according to mold materials. And surface roughness characteristics had been analysed for micro or nano mold fabrication. Si wafer, Glassy Carbon, STAVAX and DLC that have been normally considered as good micro or nano mold materials were used in the study.

• Journal of Korean Institute of Industrial Engineers
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• v.26 no.2
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• pp.171-182
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• 2000

For the last five years, data mining has drawn much attention by researchers and practitioners because of its many applicable domains. This article presents an adaptive decision tree algorithm for dynamically reasoning machine failure cause out of real-time, large-scale machine status database. Among many data mining methods, intelligent decision tree building algorithm is especially of interest in the sense that it enables the automatic generation of decision rules from the tree, facilitating the construction of expert system. On the basis of experiment using semiconductor etching machine, it has been verified that our model outperforms previously proposed decision tree models.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.