• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.50-53
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• 2002

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2004.05a
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• pp.132-137
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• 2004

반도체 소자의 마킹 / 표면 검사에 대한 적응적 reference 데이터 자동 획득 알고리즘과 검사에서의 실시간 정합 알고리즘을 개발하여, 모든 반도체 소자의 마킹 / 표면 검사에 대한 오류를 검출할 수 있는 마킹 / 표면 검사 시스템을 개발한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.51-54
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• 2003

반도체 산업의 발전에 따라 생산과정에서의 반도체 소자의 특성을 검사하고, 오류를 검출하는 작업을 효율성 있게 하여 생산성을 향상시키는 것이 더욱 중요시 되고 있다. 이러한 흐름에 맞추어 반도체 test장비에 VFCS(voltage forcing current sensing)와 CFVS(current forcing voltage sensing)를 test 할 수 있게 개발하였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.55-58
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• 2003

반도체 소자의 집적도의 발전에 따라 생산과정에서의 기능적인 오류 검사 소요시간이 증가하게 되어 비용절감에 커다란 장애 요인이 되고 있다. 이러한 문제점을 효과적으로 처리하기 위하여 일괄적인 패턴과 어드레스를 발생시키는 pattern generator를 연구하였다.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.6
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• pp.694-699
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• 2012

In this paper, semiconductor package inspection results using white light interferometer with large F.O.V., in order to apply semiconductor product inspection process, are shown. Experimental 3D data repeatability test results for the same special bumps of each substrate are shown. Experimental 3D data repeatability test results for all the bumps in each substrate are also shown. Semiconductor package inspection using white light interferometer with large F.O.V. is very important for the fast 3D data inspection in semiconductor product inspection process. This paper is surely helpful for the development of in-line type fast 3D data inspection machine.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.481-484
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• 2004

To make production and equipment investment plans in semiconductor Line, implementation of many variables is needed. But these factors could bring many changes and the result is hard to predict. Because prediction is hard, it is hard to make a standard. So this project established Semiconductor production plans using LP Algorithm to satisfy all the conditions from the factors and came up with thesis on reasonable and standardized process.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.169-176
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• 2003

Telematic and new programming technologies support the increasing demand of education and training leading to the delivery of computer based learining systems open to distance and continuing education. Using LabVIEW, we designed and implemented an interactive learning environment for practice on electronics measurement methodologies. The environment provides remote access to real and simulated instrumentation and guided experiments on basic circuits. The environment is applied to the education and training on electronics for engineers in the field of semiconductor industry.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.102-105
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• 2005

In this study Al electrode for OLED was deposited by FTS(Facing Targets Sputtering) system which can deposit thin films with low substrate damage. The Al thin films were deposited on the cell (LiF/EML/HTL/Bottom electrode) as a function of working gas such as Ar, Kr or mixed gas. Also Al thin films were prepared with working gas pressure (1, 6 mTorr ). The film thickness and I-V curve of Al/cell were evaluated by $\alpha$-step and semiconductor parameter (HP4156A) measurement.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.137-141
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• 2005

Quantum dot(QD) 메모리용 silicon nano-particle을 corona 방전방법에 의해 상온에서 대량 발생하는 방법을 개발하였다. Silicon QD는 SiH4 가스를 코로나 방전 영역을 통과시켜 발생시켰으며, 코로나 전압은 2.75kV를 사용하였다. SiH4 몰농도 $0.33{\times}10^{-7}\;mol/l$ 일 경우 발생된 QD입자 크기는 약 10nm이며 기하학적 표준편차(geometric standard deviation)는 1.31이었다. 이 조건에서 nonvolatile quantum dot semiconductor memory (NVQDM)를 제작하였으며, 이렇게 제작된 NVQDM flat band voltage는 1.5 volt였다.