• Title/Summary/Keyword: semiconductor device reliability

Search Result 122, Processing Time 0.023 seconds

Optimization of InAlAs/InGaAs HEMT Performance for Microwave Frequency Applications and Reliability

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.4 no.3
    • /
    • pp.240-249
    • /
    • 2004
  • In the present paper efforts have been made to optimize InAlAs/InGaAs HEMT by enhancing the effective gate voltage ($(V_c-V_off)$) using pulsed doped structure from uniformly doped to delta doped for microwave frequency applications and reliability. The detailed design criteria to select the proper design parameters have also been discussed in detail to exclude parallel conduction without affecting the del ice performance. Then the optimized value of $V_c-V_off$and breakdown voltages corresponding to maximum value of transconductance has been obtained. These values are then used to predict the transconductance and cut-off frequency of the del ice for different channel depths and gate lengths.

Process-Structure-Property Relationship and its Impact on Microelectronics Device Reliability and Failure Mechanism

  • Tung, Chih-Hang
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.3 no.3
    • /
    • pp.107-113
    • /
    • 2003
  • Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.

Enhancement of electrical characteristics and reliability of CuGeS2/GeS2-based super-linear-threshold-switching device by insertion of TiN liner

  • Hea-Jee Kim;Hyo-Jun Kwon;Dong-Hyun Park;Jea-Gun Park
    • Journal of the Korean Physical Society
    • /
    • v.80
    • /
    • pp.1076-1080
    • /
    • 2022
  • For preventing a sneak current in the 3D cross-point array, the selection device is essentially necessary and an n-MOSFET has been used for the selection device. However, the three-terminal electrodes of n-MOSFET make to achieve a high density of a cross-point array difficult. As a solution, using a selector having two terminal electrodes has been intensively researched. We presented that the CuGeS2/GeS2-based super-linear-threshold-switching (SLTS) selector device with the insertion of optimal TiN liner thickness exhibited outstanding electrical characteristics and reliability. The dependency of electrical characteristics and reliability on various TiN liner thicknesses were investigated. In addition, the principles of reliability and electrical characteristics improvement were understood through the energy dispersive spectroscopy elemental mapping and line profile of Cu. The adequate amount of Cu distributed in GeS2 resistive switching layer is a key factor to achieve excellent electrical characteristics and reliability for an ultra-high-density 3D cross-point array cell.

Studies on Flip Chip Underfill Process by using Molding System (몰딩공정을 응용한 플립칩 언더필 연구)

  • 한세진;정철화;차재원;서화일;김광선
    • Journal of the Semiconductor & Display Technology
    • /
    • v.1 no.1
    • /
    • pp.29-33
    • /
    • 2002
  • In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

  • PDF

Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

  • Kim, Yong-Bin
    • Transactions on Electrical and Electronic Materials
    • /
    • v.11 no.3
    • /
    • pp.93-105
    • /
    • 2010
  • Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.7 no.2
    • /
    • pp.120-131
    • /
    • 2007
  • A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

Design of Asynchronous Nonvolatile Memory Module with Self-diagnosis and Clock Function (자기진단과 시계 기능을 갖는 비동기용 불휘발성 메모리 모듈의 설계)

  • Woohyeon Shin;Kang Won Lee;Oh Yang
    • Journal of the Semiconductor & Display Technology
    • /
    • v.22 no.1
    • /
    • pp.43-48
    • /
    • 2023
  • This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

  • PDF

Differential Burn-in and Reliability Screening Policy Using Yield Information Based on Spatial Stochastic Processes (공간적 확률 과정 기반의 수율 정보를 이용한 번인과 신뢰성 검사 정책)

  • Hwang, Jung Yoon;Shim, Younghak
    • Journal of Korean Society of Industrial and Systems Engineering
    • /
    • v.35 no.4
    • /
    • pp.1-9
    • /
    • 2012
  • Decisions on reliability screening rules and burn-in policies are determined based on the estimated reliability. The variability in a semiconductor manufacturing process does not only causes quality problems but it also makes reliability estimation more complicated. This study investigates the nonuniformity characteristics of integrated circuit reliability according to defect density distribution within a wafer and between wafers then develops optimal burn-in policy based on the estimated reliability. New reliability estimation model based on yield information is developed using a spatial stochastic process. Spatial defect density variation is reflected in the reliability estimation, and the defect densities of each die location are considered as input variables of the burn-in optimization. Reliability screening and optimal burn-in policy subject to the burn-in cost minimization is examined, and numerical experiments are conducted.

Analysis and Improvement of Reliability in IGZO TFT for Next Generation Display

  • Fujii, Mami;Fuyuki, Takashi;Jung, Ji-Sim;Kwon, Jang-Yeon;Uraoka, Yukiharu
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2009.10a
    • /
    • pp.326-329
    • /
    • 2009
  • We investigated the degradation of $In_2O_3-Ga_2O_3$-ZnO (IGZO) thin-film transistors (TFTs), which is promising device for driving circuits of nextgeneration displays. We performed the electronic stress test by applying gate and drain voltage. We discussed the degradation mechanism by thermal analysis and device simulation.

  • PDF

Performance Improvement of Asynchronous Mass Memory Module Using Error Correction Code (에러 보정 코드를 이용한 비동기용 대용량 메모리 모듈의 성능 향상)

  • Ahn, Jae Hyun;Yang, Oh;Yeon, Jun Sang
    • Journal of the Semiconductor & Display Technology
    • /
    • v.19 no.3
    • /
    • pp.112-117
    • /
    • 2020
  • NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.