• Molecules and Cells
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• v.27 no.5
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• pp.497-502
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• 2009

In mouse embryos, somite formation occurs every two hours, and this periodic event is regulated by a biological clock called the segmentation clock, which involves cyclic expression of the basic helix-loop-helix gene Hes7. Hes7 expression oscillates by negative feedback and is cooperatively regulated by Fgf and Notch signaling. Both loss of expression and sustained expression of Hes7 result in severe somite fusion, suggesting that Hes7 oscillation is required for proper somite segmentation. Expression of a related gene, Hes1, also oscillates by negative feedback with a period of about two hours in many cell types such as neural progenitor cells. Hes1 is required for maintenance of neural progenitor cells, but persistent Hes1 expression inhibits proliferation and differentiation of these cells, suggesting that Hes1 oscillation is required for their proper activities. Hes1 oscillation regulates cyclic expression of the proneural gene Neurogenin2 (Ngn2) and the Notch ligand Delta1, which in turn lead to maintenance of neural progenitor cells by mutual activation of Notch signaling. Taken together, these results suggest that oscillatory expression with short periods (ultradian oscillation) plays an important role in many biological events.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.36 no.6
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• pp.621-628
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• 2018

More than four visible GPS (Global Positioning System) satellites are required to obtain absolute positioning. However, it is not easy to satisfy this condition when a rover is in such unfavorable condition as an urban area. As a consequence, clock-aided positioning has been used as an alternative method especially when the number of visible satellites is three providing that receive clock error information is available. In this study, LSC (Least-Squares Collocation) method is proposed to interpolate clock errors for clock-aided positioning after analyzing the characteristics of receiver clock errors. Numerical tests are performed by using GPS data collected at one of Korean CORS (Continuously Operating Reference Station) and a nearby GPS station. The receiver clock errors are obtained through the DGPS (Differential GPS) positioning technique and segmentation procedures are applied for efficient interpolation. Then, LSC is applied to predicted clock error at epoch which clock information is not available. The numerical test results are analyzed by examining the differences between the original and interpolated clock errors. The mean and standard deviation of the residuals are 0.24m and 0.49m, respectively. Therefore, it can be concluded that sufficient accuracy can be obtained by using the proposed method in this study.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1383-1386
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• 2001

Internet 이용자의 급격한 증가와 광대역 통신망(B-ISDN) 구축의 확산에 따라 ATM(Asynchronous Transfer Mode)망 접속장치의 큰 수요가 기대되며, 또한 ATM망 접속장치의 성능 향상도 요구되고 있다. 기존의 연구들은 컴퓨터 프로그램의 메모리에 대한 참조가 지역적이라는 특성을 이용한 가상 메모리의 효율적인 페이지 교체 알고리즘 및 캐쉬 처리 방안들이 진행되어 왔다. 본 논문은 ATM 프로토콜 프로세서를 설계하는데 있어 네트워크 트래픽의 지역성(Locality of Reference)을 고려한 캐쉬 메모리 구조를 적용하여 보다 향상된 ATM 셀 수신이 가능하도록 한다. ATM 셀의 가상 패스 식별자/가상 채널 식별자(VPI/VCI)를 캐쉬 처리함으로써, 패킷을 분해, 재조립(Segmentation and Reassembly)할 때 관련 테이블의 검색 시간을 줄일 수 있다. 캐쉬 메모리 적용으로 인한 성능 향상을 평가하기 위해 ATM NIC 프로세서와 내부 캐시 메모리 그리고, 외부 SRAM 사이에 셀 수신 정보의 Read 와 Write에 드는 시간 비용(System Clock Cycle)을 캐시의 Hit 또는 Miss 등에 따라 구분하고, 이를 기반으로 한 시뮬레이터에 3 종류의 ATM 셀 스트림을 가하여 각각에 대해 평균 셀 처리시간, 데이터 버스의 트래픽 비율 그리고, 히트율의 3가지 평가요소를 측정하고, 비교하였다.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.457-469
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• 2018

This study aimed to investigate the fundamental reasons for the presence of multi-homed host and the risks associated with such risky system. Furthermore, multi-homed host detection methods that have been researched and developed so far were compared and analyzed to determine areas for improvement. Based on the results, we propose the model of an improved automatic detection system and we implemented it. The experimental environment was configured to simulate the actual network configuration and endpoints of an organization employing network segmentation. And the functionality and performance of the detection system were finally measured while generating multi-homed hosts by category, after the developed detection system had been installed in the experiment environment. We confirmed that the system work correctly without false-positive, false-negative in the scope of this study. To the best of our knowledge, the presented detection system is the first academic work targeting multi-homed host under agent-based.