• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• International Journal of Concrete Structures and Materials
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• v.8 no.3
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• pp.251-258
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• 2014

The use of sustainable technologies such as supplementary cementitious materials, and/or recycled post-consumer environmental wastes is widely used in concrete industry in the last decade. This paper presents the results of a laboratory investigation of normal concrete containing sustainable technologies. Twenty one mixtures (21) were prepared with different combinations of silica fume, fly ash, olive's seed ash, and corncob ash (CCA). Fresh and hardened concrete properties were measured, as expected the inclusion of the sustainable technologies affected both fresh and hardened concrete properties. Based on the results obtained in this study and the analyses conducted, the following observations were drawn: replacing the cement by olive's seed ash or CCA has a significant effect on fresh concrete workability. Olive's seed ash increased the slump by more than 200 % compared to the control mixtures. The compressive strength of mixtures containing olive's seed ash showed by 45 and 75 % decrease compared to the control mixtures. The 28 days compressive strength of mixtures produced by CCA of 10 % replacement decreased by 41 % compared to the control mixture.

• The Korean Journal of Ecology
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• v.25 no.6
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• pp.395-398
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• 2002

Present paper showed allelopahtic effects of Tagetes minuta aqueous extracts on seed germination and root hair development. Allelopathy of aqueous extracts derived from T. minuta examined using two test plant species (Lotus comiculatus var. japonicus and Lactuca sativa). The seeds of test species were inoculated in petri dishes containing 0, 10,50 and 100% aqueous extracts from T. minuta. At day 5, the relative seed germination ratio to control was evaluated, and the development of seedling root hairs was observed through light microscopy. Seed germination of L. comiculatus var. japonicus was significantly inhibited proportional to the concentrations of aqueous extract, but that of L. sativa wasn't inhibited. The inhibitory allelopathic effect of T. minuta was found in the development and growth of seedling root hairs. It was concluded that the inhibitory allelophatic effects have been to be investigated using various bioassay, for the allelopathy of plant species shows species-specific and organ-specific.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 1996.06c
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• pp.679-684
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• 1996

The work was aimed at realize the problem of seed processing . Solving this problem it was ascertained that the existing mathematical methods are reliable enough, but they are used practically very seldom. The work offers to use the expert system technology which allows to solve problems connected with practical knowledge of experts in the region of investigation effectively. The method of knowledge structuring and analizing as well as technique of knowledge acquisition which is necessary for realization of this technology are worked-out in the work. As the result applying the worked-out method the prototypes of the expert system (ES) are created : -ES " Sieves " ; research prototype for the sieve choice for the seed sorting machines -ES " Diagnostics " ; displaying prototype for the technological determination of action disrepair of seed sorting machines.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1133-1136
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• 2003

This paper has been studied about the implemention of the data-encription processor and imformation security system. Also in the paper, the brief contents of the verification of the data-encryption algorithm and the method of using HDL-level sources implemented is described. And then this paper has been designed for multi-level data secure system to verify and analyze the data-encryption processor implemented as VHDL.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Korean Journal of Plant Resources
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• v.33 no.1
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• pp.33-39
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• 2020

This study was carried out to provide basic information for mass breeding and cultivating the saplings of Camellia japonica. The germination rates did not show definite tendency according to the changes of seed weight at room temperature and 4℃ dry storage conditions. The germination rate of 4℃ wet sand storage was increased with seed weight, but showed very low germination rate for 120 days of storage. The germination rate was above 80% in 60 days, 90 days and 120 days, respectively, at 4℃ wet filter paper storage conditions. The average days taken for those germinations were about 30 days at room temperature and 4℃ dry storage conditions, but wet storage (sand, filter paper) condition took the shortly nearly 13 days for those germinations. Leaf number, leaf dry weight, stem diameter and root dry weight were higher than total average by more than 1.21 g for seed weight. Stem length was higher than the average by more than 1.01 g, plant dry weight was higher than the average by more than 0.81 g, and stem dry weight was higher than the average by more than 0.61 g. In the case of seed weight becoming heavier, seedling growth was good but T/R ratio tended to decrease. In order to increase the mass production of seedlings using Camellia japonica seeds, we need to specify the weight and size of those seeds. The 4℃ wet filter paper storage condition was evaluated as the most efficient method for the seed storage used for seeding.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.