• ETRI Journal
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• 제30권2호
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• pp.344-346
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• 2008

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co-design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co-design achieves a phase noise of -130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co-design of -101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.

• ETRI Journal
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• 제28권4호
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• pp.529-532
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• 2006

This letter describes a compact printed helical resonator and its application to a microwave oscillator circuit implemented in coplanar waveguide (CPW) technology. The high quality (Q)-factor and spurious-free characteristic of the resonator contribute to the phase noise reduction and the harmonic suppression of the resulting oscillator circuit, respectively. The designed resonator showed a loaded Q-factor of 180 in a chip area of only 40% of the corresponding miniaturized hairpin resonator without any spurious resonances. The fully planar oscillator incorporated with this resonator showed an additional phase noise reduction of 10.5 dB at a 1 MHz offset and a second harmonic suppression enhancement of 6 dB when compared to those of a conventional CPW oscillator without the planar helical resonator structure.

• Journal of electromagnetic engineering and science
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• 제6권3호
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• pp.160-164
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• 2006

This paper describes a compact printed helical resonator and its application to a microwave oscillator circuit implemented in coplanar waveguide(CPW) technology. The high Q-factor and spurious-free characteristic of the resonator contribute to the phase noise reduction and the harmonic suppression of the resulting oscillator circuit, respectively. The designed resonator resonating at the frequency of 5.5 GHz showed a loaded Q of 180 in a chip area of only 40 % of the corresponding miniaturized hairpin resonator without any spurious resonances. The fully planar oscillator incorporated with this resonator showed additional phase noise reduction of 10.5 dB at 1 MHz offset and a second harmonic suppression enhancement of 6 dB when compared to those of a conventional CPW oscillator without the planar helical resonator(PHR) structure.

• 한국정보통신학회논문지
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• 제8권4호
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• pp.787-792
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• 2004

본 논문에서는 근거리무선 통신용 RF 모듈을 구성하는 핵심 부품인 5.5GHz 대역의 발진기를 설계 제작하였다. NEC사의 잡음 특성이 우수한 HJ FET인 NE3210S01를 사용하여 위상잡음 특성을 개선하였고, 구현된 회로는 HP사의 회로 시뮬레이터인 ADS2002를 사용하여 설계 및 제작하였으며 발진기의 특성을 측정한 결과, 중심 주파수 5.5 GHz에서 출력전력이 10 dBm 그리고 2차 고조파 억압이 -31 dBc이며 중심 주파수 100 kHz offset에서 -98.83 dBc의 위상잡음 특성을 얻었다. 제작된 발진기는 근거리 무선 통신용 국부 발진기로 이용될 수 있다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 춘계종합학술대회
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• pp.96-100
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• 2004

본 논문에서는 근거리무선 통신용 RF 모들을 구성하는 핵심 부품인 5.5GHz 대역의 발진기를 설계 제작하였다. NEC사의 잡음 특성이 우수한 HJ FET인 NE3210S01를 사용하여 위상잡음 특성을 개선하였고, 구현된 회로는 HP사의 회로 시뮬레이터인 ADS2002를 사용하여 설계 및 제작하였으며 발진기의 특성을 측정한 결과, 중심 주파수 5.5 GHz에서 출력전력이 10 ㏈m 그리고 2차 고조파 억압이 -31 ㏈c이며 중심 주파수 100 KHz offset에서 -98.83 ㏈c의 위상잡음 특성을 얻었다. 제작된 발진기는 근거리 무선 통신용 국부 발진기로 이용될 수 있다.

• 대한전자공학회논문지
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• 제19권3호
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• pp.37-45
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• 1982

본 논문은 변형된 디지탈 Costas loop에 관한 논문으로서 제1부의 계속이다. 본 제2부 논문에서는 시스템에 잡음이 있을 경우 그의 성능을 해석하였다. 입력신호가 white Gaussian 잡음이 첨가되면 고려되는 DPLL의 noise process는 phase error detertor의 tan-1(·)함수에 의해서 Rician이 됨을 보였다. 이 경우 Chapman-Kolmogorov 방정식을 수치적으로 풀므로써 1차와 2차 loop phase error의 steady state probability density함수, mean 및 variance를 얻었으며 이 결과를 컴퓨터 시뮬레이tus에 의해서 입중하였다.

• 한국소음진동공학회논문집
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• 제23권2호
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• pp.112-122
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• 2013

Recently the construction of stations under railway lines and railway sections passing through central area of cities are increasing, calling for an urgent establishment of countermeasures against railway vibration and its subsequent second-phase noise. Of technology developed up to now, the most efficient countermeasure is the floating slab track, a track system isolated from the sub-structure by springs. Unfortunately, however, the system design technology and technology for key components have not yet developed in Korea. As such, in this study, the analysis and design technology of floating slab track and its vibration isolator technology can be achieved. In preparation for future demands, it is expected to raise awareness for the need of technology self-support and to make a meaningful contribution to mitigating vibration and noise produced by the next-generation high-speed railway.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2013년도 춘계학술대회 논문집
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• pp.636-641
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• 2013

Recently the construction of stations under railway lines and railway sections passing through central area of cities are increasing, calling for an urgent establishment of countermeasures against railway vibration and its subsequent second-phase noise. Of technology developed up to now, the most efficient countermeasure is the floating slab track, a track system isolated from the sub-structure by springs. Unfortunately, however, the system design technology and technology for key components have not yet developed in Korea. As such, in this study, the analysis and design technology of floating slab track and its vibration isolator technology can be achieved. In preparation for future demands, it is expected to raise awareness for the need of technology self-support and to make a meaningful contribution to mitigating vibration and noise produced by the next-generation high-speed railway.

• Journal of electromagnetic engineering and science
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• 제4권4호
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• pp.156-161
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• 2004

The MMIC cascode VCO is designed, fabricated, and measured for Ku-band Low Noise Blcok(LNB) system using InGaP/GaAs HBT technology. The phase noise of -116.4 dBc/Hz at 1 MHz offset with output power of 1.3 dBm is obtained at 11.526 GHz by applying 3 V and 11 mA, which is comparatively better characteristics than compared with the different configuration VCOs fabricated with other technologies. The simulated results of oscillation frequency and second harmonic suppression agree with the measured results. The phase noise is improved due to the use of the smallest value of inductor in frequency determining network and the InGaP ledge function of the technology. The chip size of $830\time781\;{\mu}m^2$ is also achieved.

• Journal of electromagnetic engineering and science
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• 제9권1호
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• pp.25-31
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• 2009

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$\sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{\mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{\times}0.9\;mm^2$.