• Title/Summary/Keyword: scheduling feasibility

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Temperature Control of a CSTR using Fuzzy Gain Scheduling (퍼지 게인 스케쥴링을 이용한 CSTR의 온도 제어)

  • Kim, Jong-Hwa;Ko, Kang-Young;Jin, Gang-Gyoo
    • Journal of Institute of Control, Robotics and Systems
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    • v.19 no.9
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    • pp.839-845
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    • 2013
  • A CSTR (Continuous Stirred Tank Reactor) is a highly nonlinear process with varying parameters during operation. Therefore, tuning of the controller and determining the transition policy of controller parameters are required to guarantee the best performance of the CSTR for overall operating regions. In this paper, a methodology employing the 2DOF (Two-Degree-of-Freedom) PID controller, the anti-windup technique and a fuzzy gain scheduler is presented for the temperature control of the CSTR. First, both a local model and an EA (Evolutionary Algorithm) are used to tune the optimal controller parameters at each operating region by minimizing the IAE (Integral of Absolute Error). Then, a set of controller parameters are expressed as functions of the gain scheduling variable. Those functions are implemented using a set of "if-then" fuzzy rules, which is of Sugeno's form. Simulation works for reference tracking, disturbance rejecting and noise rejecting performances show the feasibility of using the proposed method.

Design and Prototype Implementation of the Curved Plates Flow Tracking and Monitoring System using RFID (RFID 기술을 이용한 곡가공 부재 추적 및 모니터링 시스템 설계 및 프로토타입의 구현)

  • Noh, Jac-Kyou;Shin, Jong-Gye
    • Korean Journal of Computational Design and Engineering
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    • v.14 no.6
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    • pp.424-433
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    • 2009
  • In order to improve productivity and efficiency of ship production process, production technology converged with Information Technology can be considered. Mid-term scheduling based on long-term schedule of ship building and execution planning based on short-term production schedule have an important role in ship production processes and techniques. However, data used in the scheduling are from the experiences of the past, cognitive, and often inaccurate, moreover the updates of the data by formatted documents are not being performed efficiently. This paper designs the tracking and monitoring system for the curved plates forming process with shop level. At first step to it, we redefine and analyze the curved plates forming process by using SysML. From the definition and analysis of the curved plates forming process, we design the system with respect to operational view considering operational environment and interactions between systems included and scenario about operation, and with respect to system view considering functionalities and interfaces of the system. In order to study the feasibility of the system designed, a prototype of the system has been implemented with 13.56 MHz RHD hardware and application software.

A study on the genetic algorithms for the scheduling of parallel computation (병렬계산의 스케쥴링에 있어서 유전자알고리즘에 관한 연구)

  • 성기석;박지혁
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1997.10a
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    • pp.166-169
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    • 1997
  • For parallel processing, the compiler partitions a loaded program into a set of tasks and makes a schedule for the tasks that will minimize parallel processing time for the loaded program. Building an optimal schedule for a given set of partitioned tasks of a program has known to be NP-complete. In this paper we introduce a GA(Genetic Algorithm)-based scheduling method in which a chromosome consists of two parts of a string which decide the number and order of tasks on each processor. An additional computation is used for feasibility constraint in the chromosome. By granularity theory, a partitioned program is categorized into coarse-grain or fine-grain types. There exist good heuristic algorithms for coarse-grain type partitioning. We suggested another GA adaptive to the coarse-grain type partitioning. The infeasibility of chromosome is overcome by the encoding and operators. The number of processors are decided while the GA find the minimum parallel processing time.

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MECHANISATION SYSTEM FOR LARGE SCALE GRAIN MAIZE PRODUCTION IN MALASIA

  • Abu-Hassan, D.;Nor, J.M.;Daham, M.D.M.
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 1993.10a
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    • pp.158-173
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    • 1993
  • The formulated mechanization packages for grain maize production have performed to the expected limit generating encouraging information. Besides physical feasibility , management factors viz ; production operation sequence, operations scheduling and machinery matching with respect to environment can still limit system suitability. A new production operation sequence was introduced to overcome weed problems and limitations of available working days. Proper operations scheduling will improve the initial soil-crop environment for better seedling establishment, and reduce the (). been identified as key factors to reduce capital investment and cost of proudction .

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Smoothly Connected Path Generation and Time-Scheduling Method for Industrial Robot Applications (산업용로봇 작업을 위한 유연한 연결경로 생성과 시간계획)

  • Lee Won-Il;Ryu Seok-Chang;Cheong Joo-No
    • Journal of Institute of Control, Robotics and Systems
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    • v.12 no.7
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    • pp.671-678
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    • 2006
  • This article proposes a smooth path generation and time scheduling method for general tasks defined by non-smooth path segments in industrial robotic applications. This method utilizes a simple 3rd order polynomial function for smooth interpolation between non-smooth path segments, so that entire task can effectively maintain constant line speed of operation. A predictor-corrector type numerical mapping technique, which correlates time based speed profile to the smoothed path in Cartesian space, is also provided. Finally simulation results show the feasibility of the proposed algorithm.

Study on Automatic Generation of Platform Configuration Register in FlexRay Protocol (FlexRay 프로토콜에서 플랫폼 구성 변수의 자동 생성에 관한 연구)

  • Yang, Jae-Sung;Park, Jee-Hun;Lee, Suk;Lee, Kyung-Chang;Choi, GwangHo
    • IEMEK Journal of Embedded Systems and Applications
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    • v.7 no.1
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    • pp.41-52
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    • 2012
  • Recently, FlexRay was developed to replace controller area network (CAN) protocol in chassis networking systems, to remedy the shortage of transmission capacity and unsatisfactory real-time transmission delay of conventional CAN. FlexRay network systems require correct synchronization and complex scheduling parameters. However, because platform configuration register (PCR) setting and message scheduling is complex and bothersome task, FlexRay is more difficult to implement in applications than CAN protocol. To assist a network designer for implementing FlexRay cluster, this paper presents an analysis of FlexRay platform configuration register and automatic generation program of PCR. To demonstrate the feasibility of the automatic generation program, we evaluated its performance using experimental testbed.

A JIT Production Scheduling in Multi-Level Parallel Machine Flow Shops (다단계 병렬기계(多段階 竝列機械) 흐름생산에서 JIT 일정계획)

  • Yoo, Chul-Soo;Lee, Young-Woo;Chung, Nam-Kee
    • IE interfaces
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    • v.7 no.3
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    • pp.171-180
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    • 1994
  • Defined is a Multi-level Parallel Machine Flow-Shop (MPMFS) which reflects some real world manufacturing situations. Just-In-Time (JIT) philosophy is applied to the MPMFS scheduling in order to achieve lowering work-in-process inventory level as well as meeting due dates. A schedule generating simulator is developed. The latest start time of each operation is determined by a backward simulation followed by another forward simulation to analyze the schedule feasibility and actual inventory level. Reasonable schedules are available through adjusting some parameters for allowance factors such as set-up times of machines and other environmental changes. The SLAMSYSTEM under Window is employed for this processing with some input/output data handling processes devised under DOS.

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Slices Analysis Method of Petri nets in FMS Using the Transitive Matrix

  • Kim, Jung-Won;Lee, Jong-Kun;Song, Yu-Jin;Kim, Jong-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.132.3-132
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    • 2001
  • In this paper, we focus on the analysis of the scheduling problem in FMS after slicing off some sub-nets using the transitive matrix. This class of Time Petri nets is obtained by merging subnets based on the machine's operations. We can divide original system into some subnets based on machine's operations using Time Petri nets slice and analyze the feasibility time in each schedules. In this paper, we show the usefulness of transitive matrix to slice off some subnets from the original net, and explain on an example.

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Scheduling Feasibility Analysis Method for RT-DEVS models (실시간 시뮬레이션을 위한 스케줄 가능성 분석 기법)

  • 조성면;김탁곤
    • Proceedings of the Korea Society for Simulation Conference
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    • 2000.11a
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    • pp.156-164
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    • 2000
  • 실시간 시뮬레이션이란 시뮬레이션 모델의 시간 진행을 실시간에 기반하여 수행하는 시뮬레이션을 말한다. 이러한 시뮬레이션은 가상 운전 교육 프로그램 또는 컴퓨터를 이용한 컨트롤 시스템의 검증 등에 사용된다. 본 논문에서는 DEVS 형식론[Zei84]을 확장한 RT-DEVS 모델의 실시간 시뮬레이션에서 주어진 모델의 스케줄링 가능성에 대한 분석 기법을 다룬다. 제한된 시스템 리소스 상에서 여러 개의 모델을 실시간에 기반하여 시뮬레이션하려면 스케줄링이 필요하다. 실시간 스케줄링 가능성을 분석하기 위하여 시뮬레이션 모델에 제한점이 주어진다. 본 논문에서는 이러한 제한점을 알아보고 이를 만족하는 시뮬레이션 모델의 상태 궤적 그래프의 합성을 통하여 전체 시뮬레이션 시스템의 스케줄링 가능성을 알아보는 기법을 제안한다.

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NoC Test Scheduling Based on a Rectangle Packing Algorithm (Rectangle Packing 방식 기반 NoC 테스트 스케쥴링)

  • Ahn Jin-Ho;Kim Gunbae;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.71-78
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    • 2006
  • An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.