• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.27-34
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• 2013

NAND Flash Memory has been used in several devices by low cost and high capacity, and the demand for mass NAND Flash Memory has increased due to the multimedia extension of mobile devices. The JFFS2, NILFS2, and YAFFS2 file systems are used mainly in NAND Flash Memory. In this paper, the performance of Sequential read/write of the 3 file systems are analyzed for the 4 I/O schedulers : CFQ(Complete Fair Queuing) I/O scheduler, NOOP(No Operation) I/O scheduler, Anticipatory I/O scheduler, and Deadline I/O scheduler. In JFFS2 file system, Anticipatory I/O scheduler has the best performance by 8% decreasing speed in writing time and 1.5% decreasing speed in reading time compared to the other I/O scheduler. In YAFFS2 file system, it results are similar to performance in reading and writing for the 4 I/O schedulers. In NILFS2 file system, NOOP I/O scheduler has 2% faster in writing and Deadline I/O scheduler has 6% faster in reading than other I/O schedulers.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.105-112
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• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.229-232
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• 2002

분간 병렬 시스템에서 사용되는 배치 작업 스케줄링 기법으로 잘 알리진 것은 Gang Scheduling과 Backfilling Scheduler가 있다. 특히 IBM SP 시스템에서 주로 사용되는 작업 스케줄러인 LoadLeveler 최신 버전에서는 이전 버전에서도 지원하였던 Backfilling Scheduler 뿐만 아니라 Gang Scheduling 기법을 새롭게 지원하게 되었다. 이에 따라 KISTI 슈퍼컴퓨팅센터에서는 슈퍼컴퓨터 3호기로 신규 도입된 IBM p690 시스템에서 LoadLeveler의 Gang Scheduling 혹은 Backfilling Scheduler 중의 한 가지 기법을 선택하여 서비스 레벨 클래스를 구현하고자 하였다. 이러한 노력의 일환으로 두 가지 스케줄링 기법을 테스트 및 분석하였다. 이에 따르면 Gang Scheduler가 개념상 여러 가지 장점을 가지므로 Backfilling Scheduler에 비하여 서비스 레벨 클래스 구성에는 용이하지만, 불완전한 구현 및 특히 CPU Utilization이 저하되는 심각한 문제점을 가지고 있었다. 따라서 Backfilling Scheduler를 통한 제한적인 서비스 레벨 클래스를 구성하기로 결론지었다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2543-2554
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• 2000

Packet schedulers for real-time communication must provide bounded delay and efficient use of network resources such as bandwidth, buffers and so on. In order to satisfy them, a large number of packet scheduling methods have been proposed. Among packet scheduling methods, an EDF (Earliest Deadline First) scheduling is the optimal one for a bounded delay service. A disadvantage of EDF scheduling is that queued packets must be sorted according to their deadlines, requiring a search operation whenever a new packet arrives at the scheduler. Although an RPQ (Rotating Priority Queue) scheduler, requiring large size of buffers, does not use such operation, it can closely approximate the schedulability of an EDF scheduler. To overcome the buffer size problem of an RPQ scheduler, this paper proposes a new scheduler named MRPQ (Multiple Rotating Priority Queue). In a MRPQ scheduler, there are several layers with a set of Queues. In a layer, Queues are configured by using a new strategy named block Queue. A MRPQ scheduler needs nearly half of buffer size required in an RPQ scheduler and produces schedulability as good as an RPQ scheduler.

• Journal of the Korea Society of Computer and Information
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• v.27 no.10
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• pp.19-28
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• 2022

In this paper, we propose the Detector Scheduler which determines the best tracking-by-detection (TBD) mechanism to perform real-time high-accurate multi-object tracking (MOT). The Detector Scheduler determines whether to run a detector by measuring the dissimilarity of features between different frames. Furthermore, we propose a self-supervision method to learn the Detector Scheduler with tracking results since it is difficult to generate ground truth (GT) for learning the Detector Scheduler. Our proposed self-supervision method generates pseudo labels on whether to run a detector when the dissimilarity of the object cardinality or appearance between frames increases. To this end, we propose the Detector Scheduling Loss to learn the Detector Scheduler. As a result, our proposed method achieves real-time high-accurate multi-object tracking by boosting the overall tracking speed while keeping the tracking accuracy at most.

• ETRI Journal
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• v.26 no.4
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• pp.351-359
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• 2004

Flow aggregation is a scalable method to provide quality of service (QoS) guarantees to a large number of flows economically. A round-robin scheduler is an efficient scheduling algorithm. We investigate flow aggregation using a round-robin scheduler and propose the use of periodic timer interrupts for rate control of the round-robin scheduler. The proposed flow aggregator is a single-stage scheduler compared to Cobb's two-stage flow aggregator consisting of an aggregator and non-aggregating scheduler. It is possible to implement flow aggregation in the existing routers with only a software upgrade. We also present a simulation study showing the delay behaviors of the proposed algorithm.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.9
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• pp.1006-1016
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• 1990

A scheduler for a class of Factory Automation (FA) systems is suggested. The technique of Timed Petri Nets is used to model FA systems and, a new concept called Unit Timed Petri Nets is proposed to schedule the system. The scheduler consists of two parts, scheduling rules and input jobs. Since flexibility should be an indispensable ingredient of the scheduler for FA systems, the method using Timed Petri Nets is adopted to represent scheduling rules in a simple and systematic manner and the scheduler is implemented with the PROLOG language. The proposed scheduler is applied to the realistic problem of flow shop.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.390-393
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• 2003

In this paper, we study on an implementation of cell scheduler which arbitrates the ATM exchange efficiently and swiftly. The designed ATM cell scheduler of this paper is based on iSLIP scheduling algorithm. It is aimed at the high-speed implementation. The implemented cell scheduler approximately provides 100% throughput for cell scheduling. We present a basic structure for cell scheduler and describe by using the HDL and perform behavior level and timing simulation. The cell scheduler of this paper is designed to support 8-port switch fabric and can expand in 32-port switch fabric. The cell scheduler for supporting the 8-port switch fabric is designed in 2-stage pipelines for the grant and accept stages respectively.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.37-43
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• 2005

A simple scheduler satisfying the proportional fairness (PF) was introduced in wireless access networks and revealed that it can achieve a good compromise between total throughput and user fairness. Though it has received much attention for some time, its application was mainly restricted to the single channel systems. In this paper, we study how to implement the PF scheduler in the multi-channel environments such as OFDMA/TDMA. Besides the traditional PF-SC scheme, we propose a new PF-OPT scheme that is the genuine PF scheduler in a sense of maximizing the total log-utility of users. The simulation results show that PF-OPT gives large throughput under the heterogeneous subchannel statistics.