• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (2)
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• pp.34-36
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• 2004

실시간 스케줄링에서 시간당 처리량을 놓이기 위해서 EDF에 SCAN기법을 추가하는 많은 방법이 연구되었다. 하지만 기존 기법들은 SCAN그룹을 생성할 때, 연속된 태스크들만 SCAN그룹의 포함 대상으로 고려하기 때문에 많은 제한이 따른다. 또한 SCAN기법은 처리방향이 고정되었기 때문에 시간적 손실이 많은 단점을 가진다. 본 연구에서는 연속되지 않은 태스크들을 SCAN그룹의 포함 대상으로 고려할 수 있는 태스크 삽입기법과, 기존의 SCAN그룹에서 합병하지 못하는 SCAN그룹들을 합병할 수 있는 SCAN합병기법, 마지막으로 SCAN그룹을 처리하는데 시간적 이점을 얻을 수 있는 양 방향 SCAN기법을 제시한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.892-895
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• 2011

SoC(System-On-Chip)을 테스트 하는 동안 소모하는 전력소모는 SoC내의 IP 코어가 증가됨에 따라 매우 중요한 요소가 되었다. 본 논문에서는 Scan Latch Reordering과 Clock Gating 기법을 적용하여 scan-in 전력소모를 줄이는 알고리즘을 제안한다. Scan vector들의 해밍거리를 최소로 하는 새로운 Scan Latch Reordering을 적용하였으며 Gated scan 셀을 사용하여 저전력을 구현하였다. ISCAS 89 벤치마크 회로에 적용하여 실험한 결과 모든 회로에 대하여 향상된 전력소모를 보였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1850-1851
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• 전기학회논문지
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• 제56권5호
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• The Journal of Advanced Prosthodontics
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• 제14권2호
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• pp.88-95
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• 2022

PURPOSE. This study investigated the accuracy of full-arch intraoral scans obtained by various scan strategies with the segmental scan and merge methods. MATERIALS AND METHODS. Seventy intraoral scans (seven scans per group) were performed using 10 scan strategies that differed in the segmental scan (1, 2, or 3 segments) and the scanning motion (straight, zigzag, or combined). The three-dimensional (3D) geometric accuracy of scan images was evaluated by comparison with a reference image in an image analysis software program, in terms of the arch shape discrepancies. Measurement parameters were the intermolar distance, interpremolar distance, anteroposterior distance, and global surface deviation. One-way analysis of variance and Tukey honestly significance difference post hoc tests were carried out to compare differences among the scan strategy groups (α = .05). RESULTS. The linear discrepancy values of intraoral scans were not different among scan strategies performed with the single scan and segmental scan methods. In general, differences in the scan motion did not show different accuracies, except for the intermolar distance measured under the scan conditions of a 3-segmental scan and zigzag motion. The global surface deviations were not different among all scan strategies. CONCLUSION. The segmental scan and merge methods using two scan parts appear to be reliable as an alternative to the single scan method for full-arch intraoral scans. When three segmental scans are involved, the accuracy of complete arch scan can be negatively affected.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1840-1841
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• 한국멀티미디어학회논문지
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• 제21권11호
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• pp.1271-1278
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• 2018

The NDT using ultrasonic is largely divided into A-Scan and C-Scan methods. Since A-Scan method is subject to subjective judgement by trained personnel, C-Scan method has been introduced, which presents the weld area in two dimensions by placing the transducers two dimensionally used in the A-Scan method. Therefore, it is necessary to develop equipment that can provide weld quality without the help of a welding expert and the presentation of effective C-Scan images. Thus, in this paper, the algorithms that express a low resolution 2-dimensional gray image formed by C-Scan method as a high-resolution color C-Scan image and automatically determine the weld quality from the generated C-Scan color image. The high resolution color C-Scan images proposed in this paper allow the exact shape of the weld point to be expressed, and an objective algorithm to use this image to automatically determine weld quality.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.221-228
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• 2007

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

• 대한디지털의료영상학회논문지
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• 제17권1호
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• pp.49-56
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• 2015

Temporal bone CT scan side skull fracture. In addition to the confirmation of the ossicles, such as fractures and dislocations, temporomandibular facial fractures, deformities surgery helps to establish a science plan. Cochlear implant surgery has been performed in the state before and after identifying purposes. Test methods are being implemented by the Conventional direct axial and Direct coronal scan, the basic method of Temporal bone CT. Helical scan is a fast Volumetric data obtained compared with the Conventional scan, the patient reduced the dose, and there are some advantages, such as reduced Beam hardening streak artifacts caused by dental fillings. This study is a comparative analysis by dose reduction for patients with a dose according to the conventional scan method and then effective from 2015 by helical scan method performed in 2014 through the retrospective survey, which was then optimized for the purpose of inspection.

• 전기학회논문지
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• 제58권1호
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.