• 한국분말야금학회:학술대회논문집
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• 한국분말야금학회 2006년도 Extended Abstracts of 2006 POWDER METALLURGY World Congress Part2
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• pp.1126-1127
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• 2006

The kinetics of sintering of Co-Fe materials was studied. The main objective was to establish the effects of iron content and sintering parameters on the microstructure and phase composition of the as-sintered material. Specimens containing from 3 to 25 wt.% iron were sintered in a dilatometer for one hour at 900, 1000 and $1150^{\circ}C$ in either hydrogen or nitrogen atmosphere. The length of specimens during the heating, hold at temperature and cooling steps were monitored to establish the sample's shrinkage. Microstructural observations were carried out on polished and etched transverse sections which were also subjected to the X-ray phase analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.1206-1208
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• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• 전자공학회논문지A
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• 제31A권3호
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• 센서학회지
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• 제3권1호
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• pp.54-60
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• 1994

본 논문에서는 멀티센서 신호처리용 집적회로를 구성하였다. 제안된 회로는 멀티센서 신호 선택을 위한 아날로그 멀티플렉서, 노이즈 제거와 신호증폭을 위한 능동 필터, 디지탈 신호처리부와의 인터페이스를 위한 샘플-홀드 회로 등으로 구성하였다. 이러한 기능회로들을 CMOS 트랜지스터로 설계하여 집적화를 가능케 하였으며, 이로 인해 멀티센서 신호처리 시스템의 저소비전력화, 소형화를 구현케하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.318-318
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• 2000

Current signal square based on switch current is presented in this article. This is the new technique that can design current signal square circuit by using switch-current memory cell, current square and sample and hold technique, which have been presented by the general switch-current. This principle which is present have the good electrical characteristics such as the low input impedance, high output impedance and high frequency response. The system can also operate in the audio frequency range to the high frequency current signal. The system application of this technique can be apply to the current signal multiplier by quarter square technique. The experimental results agree well with the theory as high accuracy and linearity.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.105-108
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• 2004

In this paper, the simple analog MPPT (Maximum Power Point Tracking) algorithm is proposed for the solar array of KOMPSAT (Korea Multi-Purpose Satellite). This method doesn't need any calculation of power by multiplication of voltage and current and a measurement of the solar array temperature. It is consist of only two sample and hold circuits, two comparators, a flip-flop, and an integrator. The proposed MPPT algorithm is verified by the simulation for the 100[W] solar array.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.125-127
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• 2005

In this paper, we propose a new scheme for the discretization of nonlinear systems using Taylor series expansion and the zero-order hold assumption. This scheme is applied to the sample-data representation of a nonlinear system with constant state tine-delay. The mathematical expressions of the discretization scheme are presented and the effect of the time-discretization method on key properties of nonlinear control system with state tine-delay, such as equilibrium properties and asymptotic ability, is examined. The proposed scheme provides a finite-dimensional representation for nonlinear systems with state time-delay enabling existing controller design techniques to be applied to then. The performance of the proposed discretization procedure is evaluated using a nonlinear system. For this nonlinear system, various sampling rates and time-delay values are considered.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.263-266
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• 한국통신학회논문지
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• 제32권10C호
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• pp.1019-1024
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• 2007

본 논문에서는 무선 랜 시스템용 10비트 20MHz 파이프라인 아날로그-디지털 변환기 설계를 위해서 Verilog-A 언어를 사용하여서 모델링하였다. 변환기내 샘플 / 홀드 증폭기, 비교기, MDAC 및 오차 보정 회로 등의 구성회로들을 각각 모델링해서 모의실험 한 결과 HSPICE를 이용한 모의 실험 시간보다 1/50배로 단축되어서 시스템 모델링에 적합함을 확인하였다.