• 제목/요약/키워드: sample and hold

검색결과 197건 처리시간 0.03초

중국(中國) 성인여성(成人女性)의 한국산(韓國産) 패션제품(製品) 인지도(認知度)에 관(關)한 연구(硏究) (A Study on the Awareness about Korean Fashion Product of Chinese Adult Women)

  • 손희순;임순;위혜정
    • 패션비즈니스
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    • 제7권1호
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    • pp.101-115
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    • 2003
  • The object of this study looks into the awareness and satisfaction about Korean fashion product of Chinese adult women inhabited in China, by comparing with foreign fashion product. The questionnaire used as a method of measurement, and the sample was 848 Chinese women from 20 to 50 age, living in China. The analysis of all data was handled by SAS(Statistical Analysis System) program, Frequency Analysis, ANOVA, Duncan's Multiple Range Test was also executed. The results from the study were as follows: 1. The preference about Korean fashion product of Chinese women is higher than American, English and Japanese fashion product, but is lower than Italy, French and Chinese fashion product in each age. 2. About the quality, design, service's satisfaction and brand reputation of Chinese adult women, Italy product is first ranked and Korean, Chinese is followed. 3. About the possession item on Korean fashion product of Chinese adult women, younger and younger chinese women on age, Ta-Ryun resident in area, a company employee on occupation hold the most. 4. About the recognition on Korean fashion product of Chinese adult women, younger and younger preferred the popularity and special design of Korean fashion product, the women inhabited in Ta-Ryun and Buk-Kyung recognized the Korean product as economical. 5. About the satisfaction on Korean fashion product of Chinese adult women, there is no significant difference on age, residential district and occupation.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • 제10권1호
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

A Novel Control Strategy of Three-phase, Four-wire UPQC for Power Quality Improvement

  • Pal, Yash;Swarup, A.;Singh, Bhim
    • Journal of Electrical Engineering and Technology
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    • 제7권1호
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    • pp.1-8
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    • 2012
  • The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

여과지가 장착된 3단 카세트를 이용한 입자상물질 채취용 펌프의 유량성능 평가방법 (Development of an Evaluation Method for Flow Rate Performance of Particulate Sampling Pump using Three-pieces Cassette Holder Containing Filters)

  • 송호준;김남희;김기연;마혜란;이광용;정지연
    • 한국산업보건학회지
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    • 제23권4호
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    • pp.348-355
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    • 2013
  • Objectives: In working environment measurement, sampling is an important stage for obtaining reliable result as analysis. A personal air sampling pump is one of the most fundamental and important element in the work environment measurement, but it remains at the level of calibrating the flow rate of the pump before and after sampling. There is no checking whether the flow rate set at the initial stage would be hold during sampling. The purpose of this study was to develop a method to evaluate the flow rate performance of particulate sampling pump with three-pieces cassette holder containing filters commonly used to sample particulate. Materials and methods: We tested back pressure of particulate sampling pumps commonly used in Korea with three-pieces cassette holder containing various filters, and tried to find out the combination conditions of filters in accordance with back pressure required by ISO standard 13137. Results: We found out the matrix of sampling media such as three-pieces cassette holder containing filters applicable to the pressure drop required by the ISO standard for evaluating the flow rate stability under increasing pressure drop and long term(8 hour) performance. Conclusions: This evaluation method using sampling media matrix for checking flow rate stability proposed by this study could be very useful tool to find out good performance pumps before sampling.

GSM 이동통신을 위한 FH 주파수 합성기 설계 및 구현에 관한 연구 (A Study on the Design and Implementation of FH Frequency Synthesizer for GSM Mobile Communication)

  • 이장호;박영철;차균현
    • 한국통신학회논문지
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    • 제17권2호
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    • pp.168-180
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    • 1992
  • 사회가 복잡 다변화 되어 감에 따라 정보전송의 거리 및 시간의 제약을 극복하기 위하여 통신기술은 끊임없이 발달해 왔다. 최근에 대부분 군·경용으로 사용되고 있는 무선 이동통신은 오늘날 기업과 개인의 요구에 따라 널리 사용되고 있으며 이동통신의 국내 수요도 점차 대중화 되어가고 있다. 이동통신에 사용되고 있는 변조기술은 AM과 FM같은 아날로그 방식이 디지털 방식으로 대체되고 있으며 이의 큰 단점은 전송대역폭의 증가이다. 그러므로 제한된 주파수 대역을 효과적으로 사용하는 것이 매우 중요하나 이에 대한 국내의 연구 및 개발은 매우 한정되어 있으나 디지털 통신의 정착을 위해 필요하다. 본 논문에서는 채널 간격 200KHz의 124개 채널을 갖는 주파수 도약 합성기의 설계를 다룬다. 합성기에 사용되는 VCO는 고순도인 신호 스펙트럼을 위해 semi-rigid 케이블을 사용했으며 하이브리드 위상검출기는 샘플-홀드검출기와 3-상태 위상 검출기를 함께 사용했다.

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A 1.8V 50-MS/s 10-bit 0.18-um CMOS Pipelined ADC without SHA

  • 어지훈;김원영;김상훈;장영찬
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 춘계학술대회
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    • pp.143-146
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    • 2011
  • 본 논문은 1.2Vpp differential 입력 범위를 가지는 50-MS/s 10-hit pipelined ADC를 소개한다. 설계된 pipelined ADC는 8단의 1.5bit/stage, 1단의 2bit/stage와 digital correction 블록, bias circuit 및 reference driver, 그리고 clock generator로 구성된다. 1.5bit/stage는 sub-ADC, DAC, gain stage로 구성된다. 특히, 설계된 pipelined ADC에서는 hardware와 power consumption을 줄이기 위해 SHA를 제거하였으며, 전체 ADC의 dynamic performance를 향상시키기 위해 linearity가 개선된 bootstrapped switch를 사용하였다. Sub-ADC를 위한 reference 전압은 외부에서 인가하지 않고 on-chip reference driver에서 발생시킨다. 제안된 pipelined ADC는 1.8V supply, $0.18{\mu}m$ 1-poly 5-metal CMOS 공정에서 설계되었으며, power decoupling capacitor를 포함하여 $0.95mm^2$의 칩 면적을 가진다. 또한, 60mW의 전력소모를 가진다. 또한, Nyquist sampling rate에서 9.3-bit의 ENOB를 나타내었다.

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Construction of core collection based on single nucleotide polymorphism analysis in soybean germplasm

  • Jeong, Namhee;Park, Soo-Kwon;Lee, Choonseok;Ok, Hyun-Choong;Kim, Dool-Yi;Kim, Jae-Hyun;Park, Ki-Do;Moon, Jung-Kyung;Kim, Namshin;Choi, Man Soo
    • 한국작물학회:학술대회논문집
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    • 한국작물학회 2017년도 9th Asian Crop Science Association conference
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    • pp.106-106
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    • 2017
  • The soybean [Glycine max (L.) Merr.] is one of the most important crop resources worldwide as food and forage. It is also important and valuable that to hold crop resources to have high genetic diversities. Recently, a core collection has been constructed in many plants to preserve the genetic resources of various plants. A core collection is small population to represent the genetic diversity of the total collection, and is of strategic importance as they allow the use of a small part of a germplasm collection that is representative of the total collection. Here, we developed the core collection consisting of 816 accessions by using approximately 180,000 (180K) single nucleotide polymorphisms (SNPs) developed in previous study. In addition, we performed genetic diversity and population structure analysis to construct the core collection from entire 4,392 collections. there were excluded sample call rates less than 93% and duplicated samples more than 99.9% according to genotype analysis using 180K SNPs from entire collections. Furthermore, we were also excluded natural hybrid resources which Glycine max and Glycine soja are mixed in half through population structure analysis. As a result, we are constructed the core collection of genetic diversity that reflects 99% of the entire collections, including 430 cultivated soybeans (Glycine max) and 386 wild soybeans (Glycine soja). The core collection developed in this study should be to provide useful materials for both soybean breeding programs and genome-wide association studies.

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UHF 대역용 Cartesian Feedback Loop 선형화 칩 설계 (Design of Cartesian Feedback Loop Linearization Chip for UHF Band)

  • 강민수;정영준;오승엽
    • 한국전자파학회논문지
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    • 제21권5호
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    • pp.510-518
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    • 2010
  • 본 논문에서는 UHF 대역(380~910 MHz)의 간이 무선 및 TRS(Trunked Radio System) 단말기에서 이용 가능한 CFL(Cartesian Feedback Loop) 선형화 칩을 Si 기반의 $0.6\;{\mu}m$ BiCMOS 공정을 이용하여 설계 및 제작한 결과를 보였다. 단말기의 송신 전력을 가변하기 위한 이득 제어 회로를 궤환 경로뿐만 아나라 순방향 경로에도 삽입함으로써 CFL의 안정성을 일정하게 유지하도록 하였으며, 무전기 PTT(Push-To-Talk) 동작에 적합하고 구현이 용이한 S/H(Sample & Hold) 구조를 이용한 DC-offset 제거 기능을 구현하였다. 송신 시험 결과, CQPSK(Compatible QPSK) 신호 인가 시, PEP(Peak Envelope Power) 3 W(34.8 dBm) 출력에서 FCC의 방사 마스크 규격을 만족함을 확인하였으며, Two-tone 인가 시, 30 dB 이상의 3차 IMD 성분 개선을 확인하였다.

센서용 Incremental 델타-시그마 아날로그 디지털 변환기 설계 (Incremental Delta-Sigma Analog to Digital Converter for Sensor)

  • 정진영;최단비;노정진
    • 전자공학회논문지
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    • 제49권10호
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    • pp.148-158
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    • 2012
  • 본 논문에서는 센서용 incremental 델타-시그마 아날로그 디지털 변환기를 설계 하였다. 회로는 크게 pre-amplifier, S & H (sample and hold) 회로, MUX와 델타-시그마 모듈레이터, 그리고 데시메이션 필터로 구성 되어 있다. 델타-시그마 모듈레이터는 3차 1-bit 구조이고 $0.18{\mu}m$ CMOS 공정을 사용 하였다. 설계된 회로는 테스트 결과 5 kHz 신호 대역에서 signal-to-noise and distortion ratio (SNDR)는 87.8 dB의 성능을 가지고, differential nonlinearity (DNL)은 ${\pm}0.25$ LSB (16-bit 기준), integral nonlinearity (INL)은 ${\pm}0.2$ LSB 이다. 델타-시그마 모듈레이터 전체 소비 전력은 $941.6{\mu}W$ 이다. 최종 16-bits 출력을 얻기 위하여 리셋을 인가하는 N cycle을 200 으로 결정하였다.

생쥐 공장 융모의 감마선 전신조사에 의한 형태학적 변화 (Morphological changes by whole-body r -irradiation in mouse jejunal villi)

  • 천기정;김진규;송치원;김무강
    • Journal of Radiation Protection and Research
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    • 제25권4호
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    • pp.217-221
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    • 2000
  • 소화기계 암의 효과적인 치료중의 하나로 방사선 치료법을 들 수 있으나 이 방법은 장 점막과 같이 빠르게 증식하는 조직에는 특히 부작용을 초래할 수 있다. 생쥐의 공장 융모가 감마선 전신 조사에 의해 형태학적으로 변화하는 정도를 관찰하였다. 생후 4주된 ICR계 생쥐를 6.5Gy와 12Gy를 전신 조사 3일 후에 공장을 채취하여 탈수 과정을 거쳐 파라핀을 입힌 조직을 절편기로 잘라 슬라이드에 부착시키고 일반적인 hematoxylin & Eosin 염색과정을 거쳐 염색후 광학현미경으로 관찰한 결과, 6.5Gy와 12Gy를 조사 받은 생쥐의 융모는 대체로 정상생쥐와 비교 할 때 융모의 길이가 짧아졌으며 융모의 두께가 비후되었고 내강은 넓어지는 경향을 나타내었다. 따라서 융모가 소화과정에 중요한 역할을 담당하며 방사선에 비교적 민감함을 나타내므로 방사선에 의한 생체영향 평가 뿐만아니라 방사선 방어제를 검색하는데 하나의 실험 파라메타가 충분히 될 수 있음을 인지하였다.

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