• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.10a
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• pp.56-60
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• 1983

There has been a great amount of interest in the design of digital filters with low sensitivity to coefficient variations. Especiaily the wave digital filter modeled after analog IC ladder filter has been studied to have low-cocfficient-sensitivity properties. This paper examined the design of the wave digital filter and how the sensitivity and roundoff noise porperty arises. As a result of computer simulation the implementation of the digital filter was possible with a lower coefficient word length comparing with the conventional cascade structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.1
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• pp.27-35
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• 1987

Digital filter suffer from roundoff noise and adder overflows due to finite word length effects. Scaling is an attempt to internal signal levels such that all signals are as large as possible, yet without the occurrence of overflows. Scaling requirements are implemented by the use of transformer. This paper proposes a procedure for scaling wave digital filters to avoid overflow problems and at the same time maximizing the output signal-to-noise ratio. Results indicate that the scaled networks have an improved signal to noise ratio over th unscaled filters under the condition that there be no overflow occuring.

• Proceedings of the Acoustical Society of Korea Conference
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• 1992.06a
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• pp.76-80
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• 1992

We consider the tapped-delay line (TDL) equalizer with the few calculation quantity and the simplity, the decision feedback equalizer (DFE) with the good property for interference, and lattice equalizer(LE) with high insensitivity to roundoff noise in mobile communication fading channel. The used adaptive algorithm is the LMS algorithm and RLS algorithm. In this paper, we have evaluated the performance of the TDL equalizer, the decision feedback equalizer, and lattice-structured equalizer, for the digital signal corrupted by the impulsive noise and the white gaussian noise under the fading channel environment. From the results of error performance analysis, it is confirmed that lattice-structured equalizer has better performance than DFE equalizer and TDL equalizer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.797-804
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• 2013

This paper presents an efficient design method of multiplierless 2-D state space digital filter based on a particle swarm optimization(PSO) algorithm. The design task is reformulated as a constrained minimization problem and is solved by our newly developed PSO algorithm. To ensure the stability of the designed 2-D state space digital filters, a stability strategy is embedded in the basic PSO algorithm. The superiority of the proposed method is demonstrated by several experiments. The results show that the approximation error and roundoff noise of the resultant filters are better than those of the digital filters which designed by recently published filter design methods. In addition, the designed filters with power-of-two coefficients have only about 1/4 computational burden of the 2-D digital filters designed in the 2's complement binary representation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.152-156
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• 1990

Making use of APF(All Pass Filter), four kinds of digital CGIC(Current-coversion Generalized Immittance Coverter) configurations have been realized, which have independent port conductances respectively. By according to hardware requirements and quantization noises generated at CGIC output due to the roundoff of the multiplier, thier performances have been compared with one another and their application method is illustrated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1236-1248
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• 1991

A new fast algorithm for computing the discrete cosine transform(DCT) Is developed decomposing N-point DCT into an N /2-point DCT and two N /4 point transforms(transpose of an N /4-point DCT. TN/t'and)It has an important characteristic that in this method, the roundoff noise power for a fixed point arithmetic can be reduced significantly with respect to the wellknown fast algorithms of Lee and Chen. since most coefficients for multiplication are distributed at the nodes close to the output and far from the input in the signal flow graph In addition, it also shows three other versions of factorization of DCT matrix with the same number of operations but with the different distributions of multiplication coefficients.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.7-12
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• 2005

Scattered look-ahead(SLA) pipelining method can be efficiently used for high-speed or low-power applications of digital II R filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large roundoff noise when the poles are crowded within some critical regions. An angle and radius constrained II R fille. design approach using modified Remez exchange algorithm and least squares algorithm is proposed to avoid tight pole-crowding in pipelined filters, resulting in improved frequency responses and reduced coefficient sensitivities. Experimental results demonstrate that our proposed method leads to chip area reduction by $33{\%}$ and low power by $45{\%}$ against the conventional method.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.