• Proceedings of the Korean Nuclear Society Conference
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• 2005.05a
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• pp.1154-1155
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• 2005

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2019.05a
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• pp.137-138
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• 2019

• ETRI Journal
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• v.29 no.3
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• pp.259-269
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• 2007

The ubiquitous flexible operating system (UbiFOS) is a real-time operating system designed for cost-conscious, low-power, small to medium-sized embedded systems such as cellular phones, MP3 players, and wearable computers. It offers efficient real-time operating system services like multi-task scheduling, memory management, inter-task communication and synchronization, and timers while keeping the kernel size to just a few to tens of kilobytes. For flexibility, UbiFOS uses various task scheduling policies such as cyclic time-slice (round-robin), priority-based preemption with round-robin, priority-based preemptive, and bitmap. When there are less than 64 tasks, bitmap scheduling is the best policy. The scheduling overhead is under 9 ${\mu}s$ on the ARM926EJ processor. UbiFOS also provides the flexibility for user to select from several inter-task communication techniques according to their applications. We ported UbiFOS on the ARM9-based DVD player (20 kB), the Calm16-based MP3 player (under 7 kB), and the ATmega128-based ubiquitous sensor node (under 6 kB). Also, we adopted the dynamic power management (DPM) scheme. Comparative experimental results show that UbiFOS could save energy up to 30% using DPM.

• Journal of IKEEE
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• v.12 no.4
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• pp.246-254
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• 2008

This paper represents a design of a 4 way SIMD processor with multi-thread and dual phase instruction pipeline. 8 threads can be performing in round-robin order, so any hazards can’t occur. The dual phase pipeline makes a pipeline operate as two pipelines, and it can fetch maximum 4 unit instructions at once. This variable length instruction set divide into first phase and second phase instructions, and with this function, complex branch and addressing can be executed at one clock cycle. This processor reduces the code size to quarter, pull out the doubled performance improvement than normal SIMD architecture.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.21-27
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• 2020

In this paper, a hybrid scheduling algorithm is proposed for CMS(Combat Management System) to improve QoS(Quality of Service) based on DWDRR(Dynamic Weighted Deficit Round Robin) and priority-based scheduling method. The main proposed scheme, DWDRR is method of packet transmission through giving weight by traffic of queue and priority. To demonstrate an usefulness of proposed algorithm through simulation, efficiency in special section of the proposed algorithm is proved. Therefore, We propose hybrid algorithm between existing algorithm and proposed algorithm. Also, to prevent frequent scheme conversion, a hysteresis method is applied. The proposed algorithm shows lower packet loss rate and delay in the same traffic than existing algorithm.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.4
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• pp.222-231
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• 2003

In This paper, the operating system using priority based round robin scheduling system is designed and implemented. Using this scheduler, Real-Time operation is possible because High priority Task is running first and the other Task is running in parallel. Also Intertask Communication, Device Driver and operating system suitable for using the compact sized embedded system were implemented. Therefore this Operating system provides efficient and rapid implementation for the compact sized embedded system application.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.135-143
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• 2006

PQ(Priority Queue) and WRR(Weighted Round Robin) are the most famous schedulers, however, these schedulers have both points of advantages and disadvantages. In this paper, we propose an algorithm that can be adopted in my kind of scheduling type with making up for weak points of PQ and WRR. The proposed algorithm includes a fuzzy theory in the scheduler to assign priorities dynamically in the DiffServ network. This algorithm produces the control discipline by the fuzzy theory to assign priorities of the Queue effectively with checking the Queue status of each class dynamically under the discipline.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.69-74
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• 2009

We propose the novel Hybrid bus arbitration policy that prevents starvation phenomenon presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitration policies. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and design overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others in the aspect of design complexity, timing margin, bus utilization, starvation prevention, request cycle and so on.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.45-53
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• 2004

This paper proposes and analyzes a new media access control (MAC) scheduling algorithm, “Interleaved Polling with Deficit Round Robin (IPDRR)” that supports weighted fairness among ONUs in Ethernet Passive Optical Network (PON). The purpose of the proposed IPDRR algerian is not only to eliminate the unused bandwidth of upstream ONU traffic, but also to provide weighted fair sharing of upstream bandwidth among ONUs in Ethernet PON systems. Simulation results show that the IPDRR improves the utilization of upstream channel by removing the unused bandwidth and provides weighted fairness among ONUs, although the IPACT scheduling is unfair according to traffic characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.46-51
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• 2010

We propose the novel Hybrid bus arbitration policy that prevents a priority monopolization presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitrations. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and area overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others and effectively controls the bus utilization.