• Proceedings of the KIPE Conference
• /
• 전력전자학회 2014년도 전력전자학술대회 논문집
• /
• pp.339-340
• /
• 2014

본 논문에서는 아답터의 크기를 소형화하기 위한 Active Valley Filler 플라이백 컨버터를 제안한다. 기존의 아답터에서 입력 전해 캐패시터는 전파 정류된 AC 전압($90{\sim}264V_{RMS}$)을 평활 시키고, 안정적으로 출력단에 에너지를 공급하기 위해 입력 에너지를 저장하는 수단으로 사용된다. 입력 전해 캐패시터는 마진이 고려되어야 하기 때문에 설계를 통해 구한 용량 및 내압보다 더 큰 값의 캐패시터가 사용되고, 이것은 아답터의 크기 증가로 이어진다. 반면, 제안 방식은 플라이백 컨버터의 입력단에 Active Valley Filler 회로를 적용하여 기존에 사용되었던 큰 크기의 입력 전해 캐패시터보다 작은 크기의 캐패시터를 사용할 수 있으므로 아답터의 소형화가 가능하다. 제안 방식의 타당성을 검증하기 위해 휴대폰 아답터용 10W급 플라이백 컨버터의 시작품을 제작하여 실험하고 그 결과를 제시한다.

• Proceedings of the KIEE Conference
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
• /
• pp.1422-1424
• /
• 2005

본 논문에서는 전원회로의 박형화에 장애가 되는 자기소자(인덕터/변압기)를 박형의 자기코어와 PCB 권선을 이용하여 박형으로 설계/제작하고 이를 역률보상회로와 서스테인 전원회로로 구성된 AC-PDP 전원회로에 적용한다. 이러한 역률보상회로와 서스테인 전원회로로 구성된 AC-PDP 전원회로를 박형자기소자, 박형커패시터 SMD소자를 이용하여 두께 30mm이하로 설계/제작하여 AC-PDP TV 시스템의 박형화 가능성을 제시한다. 또한 입력전압 90-260$V_{rms}$의 범위에서 역률개선 여부를 검증하고, 서스테인 전원회로의 부하변동에 따른 전체 AC-PDP 전원회로의 효율을 측정, 검증한다. 전원회로 각각의 구성요소에서 발생하는 전력손실을 분석하여 안정적인 AC-PDP 전원회로의 설계 가능성을 제시한다.

• The Transactions of the Korean Institute of Power Electronics
• /
• 제24권1호
• /
• pp.66-69
• /
• 2019

This study proposes a high-efficiency phase-shifted full-bridge (PSFB) converter with a wide input voltage range. The conventional PSFB converter is a useful topology in high-power applications. This converter not only achieves the zero-voltage switching of the primary switches, but also has small RMS current in the primary side. However, because the conventional PSFB converter has large freewheeling current in the primary side when it is designed considering the hold-up time of the converter, such a converter has high conduction loss at the primary switches. To solve this problem, a new PSFB converter is proposed in this study. The experiment is implemented with an input voltage ranging from a 320 V-400 V and an output power specification of 715 W.

• Fire Science and Engineering
• /
• 제34권4호
• /
• pp.1-6
• /
• 2020

In this study, the authors measured voltage and current waveforms in real time during a serial arc discharge. The analysis results of the arc discharge radiation patterns exhibited intermittent discharge, arc growth, creation of a heat generating area, occurrence of plume, and formation of a red heat area, which proceeded in that order. When the serial arc discharge was introduced, the current and voltage waveforms exhibited periodicity as sine waves. It was also observed that a restriking transient voltage occurred when the waveform changed from positive (+) to negative (-) and vice versa. When the discharge proceeded, the amount of heat generated for 1 s and 600 s was approximately 0.317 mJ, and 190 mJ, respectively. The duration of the short circuit was approximately 1.66 ms, and in the case of the voltage waveform, it was evident that the electric potential increased to 49.9 V in the same cycle. Furthermore, when the discharge proceeded, the effective value (RMS value) of the current was approximately 1.72 A with a maximum current of approximately 2.53 A, whereas the effective value of the voltage was approximately 42.8 V with a maximum of approximately 208 V.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• 제1권1호
• /
• pp.75-82
• /
• 1987

Application of conventional phase controlled power electronic circuits causes reduced power factor and increased harmonic component in the electric sources. Therefore, an Optimal PWM strategy has been investigated here in order to reduce to a large extent these effects mentioned. Optimal PWM converter has been to minimize the rms harmonic current in the sources and has been found to have a duality with Optimal PWM inverter. The voltage patterns of Optimal PWM Inverters are governed by the same switching patterns and control laws as the current patterns for Optimal PWM converter. The improvement requires switching devices having a high speed capability. While this formerly did require thyristors with force commutation circuits, today this feature is easily implemented by using power Transistor or GTOs. The control laws for minimizing the rms harmonics current in the source, the circuits and the results are shown in the paper.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• 제28권11호
• /
• pp.924-927
• /
• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

• Journal of the Korean Ceramic Society
• /
• 제39권2호
• /
• pp.120-125
• /
• 2002

AC powder EL devices were fabricated by screen printing method with the dielectric materials in insulating layer and the electrical resistivity of rear electrode. Brightness and current density were measured at voltage range of 50∼300 $V_{rms}$ to estimate optoelectrical properties of AC powder EL devices, respectively. Frequency generator was used as system producing frequency and voltage of a sine wave. Brightness and current density were measured by luminometer and multimeter. Also, dielectric constant for dielectric layer was measured by impedance analyser after preparing thick film. Dielectric constant was improved with amount of $TiO_2$ to $BaTiO_3$ powder. By applying such a process to dielectric layer of low cost AC powder EL device, brightness was improved to 50 cd/$m^2$ at similar current density. Dielectric constant $BaTiO_3$ powder by solution combustion process is better than commercial $BaTiO_3$ powder. By applying to that of low power consumption AC powder EL device, brightness was improved to 85 cd/$m^2$. Brightness of AC powder EL device was relatively decreased by control of electrical resistivity of rear electrode, current density was also decreased.

• Journal of the Korean Ceramic Society
• /
• 제38권12호
• /
• pp.1085-1092
• /
• 2001

The high efficient AC powder EL devices classified by low cost and low power consumption type fabricated using screen printing method with film thickness and organic binder. Brightness and current density were measured at frequency range of 400Hz∼1kHz and voltage range of 50∼300V$\_$rms/ to estimate optoelectrical properties of AC powder EL devices, respectively. Frequency generator was used as system producing frequency and voltage of a sine wave. Also brightness and current density were measured by luminometer and multimeter. In the case of low cost type AC powder EL device, brightness and current density were about 43 cd/m$^2$and 20$\mu$A/cm$^2$when the thickness of phosphor and dielectric layer was 45∼50$\mu$m under no addition of plasticizer respectively. In the case of low power consumption type AC powder EL device, brightness and current density were about 74 cd/m$^2$and 30∼40$\mu$A/cm$^2$when the thickness of phosphor and dielectric layer was 45∼50$\mu$m and 15∼20$\mu$m under addition of 15wt% plasticizer respectively. Also, AC powder EL device fabricated in this study showed absolutely excellent characteristics as the lifetime was longer than products of other company.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제42권9호
• /
• pp.35-40
• /
• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제40권6호
• /
• pp.408-420
• /
• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.