• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.256-262
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• 2002

This paper presents a novel radix-4 modular multiplication algorithm based on the sign estimation technique (3). The sign estimation technique detects the sign of a number represented in the form of a carry-sum pair. It can be implemented with 5-bit carry look-ahead adder. The hardware speed of the cryptosystem is dependent on the performance modular multiplication of large numbers. Our algorithm requires only (n/2+3) clock cycle for n bit modulus in performing modular multiplication. Our algorithm out-performs existing algorithm in terms of required clock cycles by a half, It is efficient for modular exponentiation with large modulus used in RSA cryptosystem. Also, we use high-speed adder (7) instead of CPA (Carry Propagation Adder) for modular multiplication hardware performance in fecal stage of CSA (Carry Save Adder) output. We apply RL (Right-and-Left) binary method for modular exponentiation because the number of clock cycles required to complete the modular exponentiation takes n cycles. Thus, One 1024-bit RSA operation can be done after n(n/2+3) clock cycles.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.127-132
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• 2007

This paper proposed receding methods for a radix-${\gamma}$ representation of the secret scalar which are resistant to SPA. Unlike existing receding method, these receding methods are left-to-right so they can be interleaved with a left-to-right scalar multiplication, removing the need to store both the scalar and its receding. Hence, these left-to-right methods are suitable for implementing on memory limited devices such as smart cards and sensor nodes

• Journal of the Chungcheong Mathematical Society
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• v.26 no.2
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• pp.297-308
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• 2013

We define one-sided quadrangular fuzzy sets, a left quadrangular fuzzy set and a right quadrangular fuzzy set. And then we generalize the results of addition, subtraction, multiplication, and division based on the Zadeh's extension principle for two one-sided quadrangular fuzzy sets. In addtion, we find the condition that the result of addition or subtraction for two one-sided quadrangular fuzzy sets becomes a triangular fuzzy number.

• Journal of the Korean Mathematical Society
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• v.42 no.4
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• pp.635-653
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• 2005

We study the distribution of a dense orbit of a lattice A acting by the right multiplication on the space $\Gamma/G$ where G is a connected simple Lie group and $\Gamma$ its lattice. We show that for $G=SL_n(\mathbb{R})$, every dense orbit is equidistributed with respect to the Euclidean norm.

• Journal of the Chungcheong Mathematical Society
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• v.33 no.3
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• pp.365-374
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• 2020

Given a noncompact semisimple Lie group G and its maximal compact Lie subgroup K such that the right multiplication of each element in K gives an isometry on G, consider a principal bundle G → G/K, which is a Riemannian submersion. We study the infinitesimal holonomy isometries. Given a closed curve at eK in the base space G/K, consider the holonomy displacement of e by the horizontal lifting of the curve. We prove that the correspondence is continuous.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.41-47
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• 2016

The times of multiplication for encryption and decryption of cryptosystem is primarily determined by implementation efficiency of the modular exponentiation of $a^b$(mod m). The most frequently used among standard modular exponentiation methods is a standard binary method, of which n-ary($2{\leq}n{\leq}6$) is most popular. The n-ary($1{\leq}n{\leq}6$) is a square-and-multiply method which partitions $b=b_kb_{k-1}{\cdots}b_1b_{0(2)}$ into n fixed bits from right to left and squares n times and multiplies bit values. This paper proposes a variable-length partition algorithm that partitions $b_{k-1}{\cdots}b_1b_{0(2)}$ from left to right. The proposed algorithm has proved to reduce the multiplication frequency of the fixed-length partition n-ary method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of Korean Medicine Rehabilitation
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• v.26 no.1
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• pp.1-11
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• 2016

Objectives The purpose of this study was to investigate the effect of Hyulboochucke-tang on the collagenase induced intracerebral hemorrhage in white rats. Methods To identify the effect of the Hyulboochucke-tang on intracerebral hemorrhage, intracerebral hemorrhage was induced in the right caudate nuclei of white rats. For normal group (n=12) and comparative group (n=12), saline was dosed, and vaccum evaporated Hyulboochucke-tang extract was dosed to treatment group (n=12), 3 and 10 days after the collagenase injection, the body weight, the brain weight, the size of hematoma, the size of the area of malacia, the number of apoptotic cell and the change in pathological histology were observed. Results 3 days after the injection, the brain weight(g) was considerably decreased in treatment group (n=12) compared to comparative group (n=12). The brain weight after 10 days of the injection was also considerably decreased in treatment group (n=6) against comparative group (n=6). The cross section(mm) of cerebral malacia after 10 days of the injection was considerably decreased in treatment group (n=6) compared to comparative group (n=6). The number of apoptotic cell in normal intracerebral around the area of malacia did not show considerable change between treatment group and comparative group. 12 days after the injection, the multiplication of gitter cells, astrocyte and newly formed capillaries around the area of malacia was distinct. Conclusions On the basis of these results, We sugggest that Hyulboochucke-tang controls swelling caused by hemorrhage and contributes to absorption of hematoma by multiplication of newly formed capillaries and recovery of damaged cerebral tissue by multiplication of gitter cells and astrocyte.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.30-37
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• 2007

An exponentiation in $GF(2^m)$ is a basic operation for several algorithms used in cryptography, digital signal processing, error-correction code and so on. Existing hardware implementations for the exponentiation operation organize by Right-to-Left method since a merit of parallel circuit. Our paper proposes a polynomial exponentiation structure with a trinomial that is organized by Left-to-Right method and that utilizes a weakly dual basis. The basic idea of our method is to decrease time delay using precomputation tables because one of two inputs in the Left-to-Right method is fixed. Since $T_{sqr}$ (squarer time delay) + $T_{mul}$(multiplier time delay) of ow method is smaller than $T_{mul}$ of existing methods, our method reduces time delays of existing Left-to-Right and Right-to-Left methods by each 17%, 10% for $x^m+x+1$ (irreducible polynomial), by each 21%, 9% $x^m+x^k+1(1, by each 15%, 1% for $x^m+x^{m/2}+1$.