• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Journal of Internet Computing and Services
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• v.9 no.1
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• pp.55-67
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• 2008

This paper presents the assignment motion algorithm unrestricted for code optimization computationally. So, this algorithm is suppressed the unnecessary code motion in order to avoid the superfluous register pressure, we propose the assignment motion algorithm added to the final optimization phase. This paper improves an ambiguous meaning of the predicate. For mixing the basic block level analysis with the instruction level analysis, an ambiguity occurred in Knoop's algorithm. Also, we eliminate an ambiguity of it. Our proposal algorithm improves the runtime efficiency of a program by avoiding the unnecessary recomputations and reexecutions of expressions and assignment statements.

• The KIPS Transactions:PartA
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• v.8A no.1
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• pp.27-35
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• 2001

This paper presents the assignment motion algorithm unrestricted for code optimization computationally. So, this algorithm is suppressed the unnecessary code motion in order to avoid the superfluous register pressure, we propose the assignment motion algorithm added to the final optimization phase. This paper improves an ambiguous meaning of the predicated. For mixing the basic block level analysis with the instruction level analysis, an ambiguity occurred in knoop’s algorithm. Also, we eliminate an ambiguity of it. Our proposal algorithm improves the runtime efficiency of a program by avoiding the unnecessary recomputations and reexecutions of expressions and assignment statements.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.359-367
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• 2005

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1227-1235
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• 2000

In this paper, we propose new concepts that the distributed counter value with the distributed EC system identify each user who users the distributed system. The web user should register his/her own user ID in the cyber shopping mall system. Instead of registration, this paper proposes the proprietary mechanism that is distributing counter. The counter assigns the distinguished number to each client. The distributed lock algorithm is used for mutual assignment of the counter to each client. The proposed algorithm is the best solution in the distributed environment system such as cyber shopping mall. If a user should register his/her own ID in every EC system, he/she may not try to use these uncomfortable systems. The mutual counter is used to identify each client. All of these features are designed and implemented on Windows NT web server. Also these features were experiments with 5 clients for 300 times. According to the experiments, clients have their own mutual counter value. The proposed algorithm will be more efficient in internet application environment. Moreover, it will improve the number of internet users.

• Journal of the Korean Society for information Management
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• v.20 no.3
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• pp.241-259
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• 2003

The Basic Semantic Register(BSR) is and official ISO register designed for interoperability among eBusiness and EDI systems. The entities registered in the current BSR are not defined in a machine-understandable way, which renders automatic extraction of structural and relationship information from the register impossible. The purpose of this study is to offer a framework for designing an ontology that can provide semantic interoperability among BSR-based systems by defining data structures and relationships with RDF and OWL, similar meaning by the 'equivalentClass' construct in OWL, the hierachical relationships among classes by the 'subClassOf' construct in RDF schema, definition of any entities in BSR by the 'label' construct in RDF schema, specification of usage guidelines by the 'comment' construct in RDF schema, assignment of classes to BSU's by the 'domain' construct in RDF schema, specification of data types of BSU's by the 'range' construct in RDF schema. Hierarchical relationships among properties in BSR can be expressed using the 'subPropertyOf' in RDF schema. Progress in semantic interoperability can be expected among BSR-based systems through applications of semantic web technology suggested in this study.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.4
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• pp.7-13
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• 1978

This paper is concerned with the realization of sequential machines using shift-register modules as their memory elements. Other methods were to select shift-registers under the specific conditions and didn't consider the complexity of combinational circuits driving them. By using an integer valued function, all shift-registers with minimum length could be selected and an optimum assignment with lowest complexity could be obtained by comparing the number of input lines of combinational logic circuits driving them.