• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.166-171
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• 2003

In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.1-8
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• 2000

Prepass code scheduling(code scheduling before register allocation), the register lifetimes may be lengthened, which may increase the amount of data dependence relations. So, it makes difficult to allocate the registers because of complex interference graph. In this paper, to improve that defect, propose an 2-phase coloring method. At first phase-1 assign the registers to variables which have long live ranges. Secondly, phase-2 allocate the registers to remained variables to minimize the register allocation cost. Experimental results shown that proposed method is more efficient scheme than Chaitin's scheme when prepass code scheduling.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.230-237
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• 1987

This paper proposes a compatible variables scheduling algorithm, which is the process to pack variables into same register without modifying program semantics, for efficient register allocation of microprogram. The algorithm constructs T-V matrix, obtains incompatible variable set and scheduling priority, and schedules compatible groups. By this algorithm, the number of compatible groups can be minimized. The algorithm was implemented with C language on VAX-11/780 computer. By applying the algorithm to practical microprograms, the effectiveness of the algorithm is verified.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1303-1310
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• 1990

This paper describes the design and implementation of a system for automatic data path synthesis in digital system. There are four subtasks to synthesize a digital system: scheduling, register allocation, functional unit allocation and bus allocation. In this paper, force directed algorithm is used for the scheduling while new algorithms are proposed for the allocation subtasks. Synthesis results of two experimental data paths including MC6502 have shown that our proposed algorithm out goes most of previous works.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.10a
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• pp.138-143
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• 1985

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.3
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• pp.95-99
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• 2008

This paper proposes a new minimal resource high-level synthesis algorithm for low power design automation. The proposed algorithm executes an efficient approach to minimize the power consumption of the functional units in a circuit during the high level synthesis. In this paper, we visit all control steps one by one to reduce the switching activity in CDFG. The register sharing algorithm determines the minimum register after the life time analysis of all variable. According to property of input signal for functional unit, the proposed method visits all control step one by one and determines the resource allocation with minimal power consumption at each control step in a greedy fashion. The effect of the proposed algorithm has been proved through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low rover.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.100-103
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• 2001

The best solution to improve the execution speed of Java program is to make use of the high speed JVM(Java Virtual Machine). The performance of JVM depends on the difference of its implementation. One of the technologies to enhance JVM performance is a JIT(Just-in-Time) code generator. The JIT code generator transforms Java byte code to the native machine code in accordance with computer system platform. The native machine code is faster than the existing interpreter method, since it can reduce the time to analyze the Java byte code. But the JIT code generator have the problem of increasing the traffic between stack and register because of using many register. Therefore, this paper suggests how to reduce the traffic by applying the policy of stack allocation to JIT code generation, as one of the methods to enhance the performance of JVM.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.3
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• pp.165-173
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• 2007

In this paper, we propose a new minimum resources allocation algorithm for optimal design automation. In the proposed algorithm, the operation are allocated to functional units so that the number of interconnection wires between functional units can be minimized. The registers are allocated to the maximal clusters generated by the minimal cluster partitioning algorithm. Finally, the interconnection is minimized by removing the duplicated inputs of multiplexers and exchanging the inputs across multiplexers. The efficiency of the proposed allocation algorithm is shown by experiments using benchmark examples.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.