• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1211-1220
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• 1990

This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1564-1574
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• 1999

In order to improve the efficiency of optimizing compilers, integration of register allocation and instruction scheduling has been extensively studied. One of the promising integration techniques is register allocation based on register-reuse chains. However, the generation of register-reuse chains in the previous approach was not completely systematic and consequently it creates unnecessarily dependencies that restrict instruction scheduling. This paper proposes a new register allocation technique based on a systematic generation of register-reuse chains. The first phase of the proposed technique is to generate register-reuse chains that are optimal in the sense that no additional dependencies are created. Thus, register allocation can be done without restricting instruction scheduling. For the case when the optimal register-reuse chains require more than available registers, the second phase reduces the number of required registers by merging the register-reuse chains. Chain merging always generates additional dependencies and consequently enforces the execution order of instructions. A heuristic is developed for the second phase in order to reduce additional dependencies created by merging chains. For matrix multiplication program, the number of registers resulting from the first phase is small enough to fit into available registers for most basic blocks. In addition, it is shown that the restriction to instruction scheduling is reduced by the proposed merging heuristic of the second phase.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.302-305
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• 2000

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.51-54
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• 2000

In this paper, an compiler system is ported and modified for register allocation experiments. This compiler system will enable various global register allocation. Lcc is introduced and Chaitin's graph coloring algorithm is executed with cmcc on DEC ALPHA 255/300. Several functions of SPEC921NT is used as inputs of the compiler system.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.497-511
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• 1999

Recently, many parallel processing technologies were developed, ILP(Instruction level Parallelism) processor's performance have been growed very rapidly. especially, EPIC(Explicitly Parallel Instruction computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.494-496
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• 2013

In this paper, we introduce a technique for delayed deallocation of temporary register allocation. We achieve faster binary translation that is used in the context of register allocation. By delaying deallocation of the temporary register containing the value, it is preserved until the next instruction fetched. If subsequent instruction does not require the value again, binary translator deallocate and release the temporary register at the first stage of the next instruction.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1255-1262
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• 2000

This paper proposes a hardware allocation and binding algorithm for ASIC Design. The proposed algorithm works on schedules input graph and simultaneously allocates and binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Especially, he register allocation is executes the allocation optimal using graph coloring. This paper shows the effectiveness of the algorithm by comparing experiments to determine number of functional unit and register in advance or to separate executing allocation and binding of existing system.