• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.421-423
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• 2005

A bootstrap circuit for floating power supply has the advantage of being simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. Hence, this paper deals with a design of charge pump circuit for a floating gate power supply of an IPM. The operation of the proposed circuit applied by three-phase inverter system for driving induction motor are verified through the experiments.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.387-390
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• 2007

Advanced-MVA(A-MVA) for LCD-TV application was proposed to yield high performance LCD-TV. By utilizing Additional Refresh Technology(ART), which has 2-TFTs but with single source and gate line only. The A-MVA can yield low color washout, fast response, and optimized brightness. AMVA has become the promising solution of advanced LCDTV panels for mass-production.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.31-37
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• 2020

We present an approximate DRAM architecture for energy-efficient deep learning. Our key premise is that by bounding memory errors to non-critical information, we can significantly reduce DRAM refresh energy without compromising recognition accuracy of deep neural networks. To validate the key premise, we make extensive Monte-Carlo simulations for several well-known convolutional neural networks such as LeNet, ConvNet and AlexNet with the input of MINIST, CIFAR-10, and ImageNet, respectively. We assume that the highest-order 8-bits (in single precision) and 4-bits (in half precision) are protected from retention errors under the proposed architecture and then, randomly inject bit-errors to unprotected bits with various bit-error-rates. Here, recognition accuracies of the above convolutional neural networks are successfully maintained up to the 10^-5-order bit-error-rate. We simulate DRAM energy during inference of the above convolutional neural networks, where the proposed architecture shows the possibility of considerable energy saving up to 10 ~ 37.5% of total DRAM energy.

• ETRI Journal
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• 제37권4호
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.321-322
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• 2007

When use FMO by error resilience purpose in existing $TYPE1{\sim}2$ compare. But, in This paper, TYPE $3{\sim}5$[Gradual decoder refresh tool] is used as error resilence tool. Experiment result, it shows that Y PSNR improves that use suitable TYPE's FMO. Images using in an experiment had better use Type $3{\sim}5$. Differ with existing paper, dipersed mode appeared result badly. Because spatial correlation is low, acted adversely in intra predication.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2001년도 춘계학술발표논문집 (상)
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• pp.19-22
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• 2001

웹 문서 표준어인 XML의 등장으로 앞으로 웹 상에 수많은 XML 문서가 존재할 것이며, 이들에 대한 효율적인 검색 기법이 요구된다. 그 중 하나로 웹 상에 산재된 XML 문서들을 여과 및 통합할 수 있는 뷰의 기능이 필요하다. 뷰의 구현 기법으로는 전통적인 질의 변경 기법과 실체 뷰 기법 등이 있다. 본 논문에서는 XML 문서를 대상으로 하는 실체 뷰에 관한 것으로, XML 문서가 변경되었을 경우에 XML 실체 뷰에 대해 점진적 갱신을 지원하는 XML 실체 뷰 관리 프레임워크(framework)에서, 실체 뷰를 통한 뷰 제공의 성능을 질의 변경 기법의 성능과 비교하여 분석한 후 실체 뷰 기법이 질의 변경 기법 보다 효율적일 수 있는 조건을 구한다.

• 정보처리학회논문지C
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• 제18C권4호
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• pp.237-242
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• 2011

LTE/SAE는 공격자의 키 획득 및 공격에 노출된 네트워크를 방지하기 위해 핸드오버 키 관리기법을 정의하고 있다. 본 논문에서는, 핸드오버 키 관리 기법이 비동기화 공격에 의해 전방향안전성이 보장되지 못 함을 보인다. 비동기화 공격을 방지하기 위해, 주기적인 루트키 갱신이 요구된다. 이에 본 논문에서는 시그널링 부하와, 공격에 노출되는 패킷의 양을 최소화 하는 최적 루트키 갱신 주기를 도출하고자 한다.

• 전자통신동향분석
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• 제34권2호
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• pp.10-18
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• 2019

Since the introduction of CRT(Cathode Ray Tube) in the 1950s, display technologies have been developed continuously. Flat panel displays such as PDP(Plasma Display Panel) and LCD(Liquid Crystal Display) were commercialized in the late 1990s, and OLED(Organic Light Emitting Diodes) and Micro-LED(Micro-Light Emitting Diodes) are now being developed and are becoming widespread. In the future, we expect to develop ultra-realistic, flexible, embedded sensor displays. Ultra-realistic display can be applied to AR/VR(Augmented Reality/Virtual Reality) devices and spatial light modulators for holography. The sensor-embedded display can be applied to robots; electronic skin; and security devices, including iris recognition sensors, fingerprint recognition sensors, and tactile sensors. AR/VR technology must be developed to meet technical requirements such as viewing angle, resolution, and refresh rate. Holography requires optical modulation technology that can significantly improve resolution, viewing angle, and modulation method to enable wide-view and high-quality hologram stereoscopic images. For electronic skin, stable mass production technology, large-area arrays, and system integration technologies should be developed.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2013년도 춘계학술발표대회
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• pp.21-23
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• 2013

Static Random Access Memory (SRAM) using CMOS technology has many advantages. It does not need to refresh every certain time, as a result, the speed of SRAM is faster than Dynamic Random Access Memory (DRAM). This is the reason why SRAM is widely used in almost processors and system on chips (SoC) which require high processing speed. Two basic operations of SRAM are read and write. We consider two basic factors, including the accuracy of read and write operations and the speed of these operations. In our paper, we propose the read and write assist circuits for SRAM. By adding a power control circuit in SRAM, the write operation performed successfully with low error ratio. Moreover, the value in memory cells can be read correctly using the proposed pre-charge method.

• 국제학술발표논문집
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• The 7th International Conference on Construction Engineering and Project Management Summit Forum on Sustainable Construction and Management
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• pp.124-132
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• 2017

This paper describes the Around View Monitoring (AVM) system for hydraulic excavators that prevents the safety accidents caused by blind spots and increases the operational efficiency. To verify the developed system, experiments were conducted with its prototype. The experimental results demonstrate its applicability in the field with the following values: 7m of a visual range, 15fps of image refresh rate, 300ms of working information data reception rate, and 300ms of surface condition data reception rate.