• Title/Summary/Keyword: redundant data

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Design of a High Speed and Low Power CMOS Demultiplexer Using Redundant Multi-Valued Logic (Redundant Multi-Valued Logic을 이용한 고속 및 저전력 CMOS Demultiplexer 설계)

  • Kim, Tae-Sang;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.148-151
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    • 2005
  • This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

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Design of a 9 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued logic (Redundant 다치논리 (Multi-Valued Logic)를 이용한 9 Gb/s CMOS 디멀티플렉서 설계)

  • Ahn, Sun-Hong;Kim, Jeong-Beom
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.121-126
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    • 2007
  • This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

Design of a 20 Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic (중복 다치논리를 이용한 20 Gb/s CMOS 디멀티플렉서 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.3
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    • pp.135-140
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    • 2008
  • This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

Implementation of CMOS 4.5 Gb/s interface circuit for High Speed Communication (고속 통신용 CMOS 4.5 Gb/s 인터페이스 회로 구현)

  • Kim, Tae-Sang;Kim, Jeong-Beom
    • Journal of IKEEE
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    • v.10 no.2 s.19
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    • pp.128-133
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    • 2006
  • This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

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Implementation and evaluation of lost packet recovery using low-bitrate redundant audio data (저비트율 잉여오디오 정보를 이용한 손실 패킷 복구 방법의 구현 및 성능 평가)

  • 박준석;고대식
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.7
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    • pp.1-5
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    • 1998
  • In this paper, recovery method with high-bitrate and low-bitrate coder was implemented in order to recover consecutive packet loss over the Internet. LPC was used as redundant audio data for recover of lost packets and RTP parcket format was modified for accommodation of redundant data. In measuring results using random packet loss rate with three redundant datra in every packet, it has shown that recovery rate was 80% in los rate of 50%. Since the processing delay for recovery of the lost packet was 200ms, this recovery method can be applied to real-time Internet sevice such as Internet phone.

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Implementation of High Speed Router's Redundancy Architecture (고속 네트워크 시스템의 이중화 회로 구현)

  • 강덕기;이상우;이준철;이형섭;이영천
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.267-270
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    • 2000
  • In this paper, we consider the simple redundant structures with the function of hardware based active/standby control. The system includes two switch modules. The switch module is connected to a data bus, but only the active switch module has control of the data bus. The standby unit takes over the function of the active unit when the active unit failure or mode command are asserted. And this paper illustrate the high-speed router system and the overall redundant system architecture. The proposed redundant architecture for 80G Router system is verified and implemented with experiment.

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Elimination of the Redundant Sensor Data using the Mobile Agent Middleware (이동 에이전트 미들웨어를 이용한 중복 센서 데이터 제거)

  • Lee, Jeong-Su;Lee, Yon-Sik
    • Journal of Internet Computing and Services
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    • v.12 no.3
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    • pp.27-36
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    • 2011
  • The sensor nodes of sensor network system are capable of wireless communication with sink nodes. They also acquire and transmit sensor data in broad region where people cannot access easily. However, the transmission of redundant data from sensor nodes reduces the lifetime of the entire system and substantial amount of resulted data needs to be resorted before implementing them to the specific applications. In this paper, the mobile agent middleware to eliminate the redundant sensor data is designed and implemented. In the proposed system, the mobile agent visits the destination sensor nodes according to the migration list offered by the meta table in the name space of the naming agent, eliminates the redundant sensor data corresponding to user condition, and acquires and transmits sensor data according to the purpose and needs. Thus, the excess transmission of the sensor data is avoided and the lifetime of the entire system can be extended. Moreover, the experiments using the mobile agent middleware with the conditions and limitations that are possible in real situation ore done to verify the successful elimination of the redundant sensor data and the efficiency of the data acquisition. Also, we show the potential applicability of the mobile agent middleware in various active sensor networks through the active rule based mobile agent middleware or the interaction with the active rule system.

Distributed Data Recording on the Optical Disks using LDPC Codes (광학 저장 매체상에 LDPC 코드를 이용한 데이터의 분산 기록 방법)

  • Kim, Tae-Woong;Ryu, Jun-Kil;Park, Chan-Ik
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.9
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    • pp.710-714
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    • 2009
  • Optical discs' capacity has increased. In case of Blu-Disc, it can store data up to 25 GB. Due to the large capacity, it can substitute tape devices for the use of backup. However, optical discs' surfaces are exposed so that it can lose data easily by exterior damages like scratches. Therefore additional reliability must be provided to maintain data for a long time. In this paper, we suggest a writing technique that gives optical discs additional reliability. Redundant data, generated by LDPC codes, are stored in disc along with the original data. These original data and redundant data are scattered over the disc to avoid losing a large part of data with one scratch. By deploying data with the distance that provides the reliability a user wants, we can enhance optical discs' reliability.

A Dynamic Packet Recovery Mechanism for Realtime Service in Mobile Computing Environments

  • Park, Kwang-Roh;Oh, Yeun-Joo;Lim, Kyung-Shik;Cho, Kyoung-Rok
    • ETRI Journal
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    • v.25 no.5
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    • pp.356-368
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    • 2003
  • This paper analyzes the characteristics of packet losses in mobile computing environments based on the Gilbert model and then describes a mechanism that can recover the lost audio packets using redundant data. Using information periodically reported by a receiver, the sender dynamically adjusts the amount and offset values of redundant data with the constraint of minimizing the bandwidth consumption of wireless links. Since mobile computing environments can be often characterized by frequent and consecutive packet losses, loss recovery mechanism need to deal efficiently with both random and consecutive packet losses. To achieve this, the suggested mechanism uses relatively large, discontinuous exponential offset values. That gives the same effect as using both the sequential and interleaving redundant information. To verify the effectiveness of the mechanism, we extended and implemented RTP/RTCP and applications. The experimental results show that our mechanism, with an exponential offset, achieves a remarkably low complete packet loss rate and adapts dynamically to the fluctuation of the packet loss pattern in mobile computing environments.

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Redundant rule Detection for Software-Defined Networking

  • Su, Jian;Xu, Ruoyu;Yu, ShiMing;Wang, BaoWei;Wang, Jiuru
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.6
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    • pp.2735-2751
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    • 2020
  • The emergence of Software Defined Networking (SDN) overcomes the limitations of traditional networking architectures. There are some advantages in SDN which are centralized global network view, programmability, and separation of the data plane and control plane. Due to the limitation of data plane storage capacity in SDN, it is necessary to process the redundancy rules of switch. In this paper, we propose a method for active detection and processing of redundant rules. We use the result generated by the customized probe package to detect redundant rules. And by checking the forwarding behavior of probe packets in the data plane, the redundancy rules are further processed. Furthermore, in order to quickly check the dynamic networks, we propose an incremental algorithms for rapidly evolve the network strategies. We conduct simulation experiments on Matlab to verify the feasibility of the algorithm. The influence of some parameters on the result are discussed.