• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.29-38
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• 1999

This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.541-544
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• 2004

This paper presents a new circuit panitioning algorithm using wire redundancy removal. This algorithm consist of the two steps. In the first step. We propose a new IIP(Iterative Improvement Partitioning) technique that selects the method to choice cells according to improvement status using two kinds of bucket structures, the one kept by total gain, and the other by updated gain. In the second step, we select the target wire in the cut-set. We add a alternative wire in the circuit to remove the target wire. For this we use wire redundancy removal and addition method The experimental results on MCNC benchmark circuits show improvement up to $41-50\%$ in cut-size over previous algorithms

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.21-29
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• 1997

This paper describes implementation contents contents of manual/automatic complex redundancy control mothod for control of a modulation system of a Paging earth station in redundancy stracture. The existed redundancy control method usually is a automatic local control method in which the redundancy switching, including display or alarm beeping through operation of display devices or audio devices, is performed by the co-action of components or modules when the abnormal status is occurred in a modulation system. However, this method introduced in here is designed to enable use of three control modes;1) Manual mode by an operator, 2) Auto-remote mode by the Network Maagement System, through implementation of the redundancy control system composed of the redundancy control board and the redundancy switching circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.138-144
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• 1989

In this paper, a new method is proposed to remove the logical redundancy for the gate-level circuit optimization. In this method, only the fanout-branch signals in the circuits, not all the signals, are examined for redundancy. When a signal is determined to be nonredundant, other nonredundant signals are found out by the efficient procedure, using only the informations which are generated in the course of the redundancy-check. In order to avoid the re-examination of a signal for redudancy, a heuristic method is proposed to determine the redundancy-checking order of signals. The proposed method is heuristic, based on the VLSI test theory. It is much faster than other methods, since it does not reexamine a signal for redundancy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.4
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.131-136
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• 1990

In this paper, new methods are proposed which speed up the logical redundancy identification for the gate-level logic optimization. Redundancy indentification, as well as deterministic test pattern generation, can be viewed as a finite space search problem, of which execution time depends on the size of the search space. For the purpose of efficient search, we propose dynamic head line and mandatory assignment. Dynamic head lines are changed dynamically in the process of the redundancy identification. Mandatory assignement can avoid unnecessary assignment. They can reduce the search size efficiently. Especially they can be used even though the circuit is modified in the optimization procedure, that is different from the test pattern generation methods. Some experimental results are presented indicating that the proposed methods are faster than existing methods.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of Ocean Engineering and Technology
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• v.29 no.5
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• pp.380-385
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• 2015

In the development of an underwater construction robot, the reliability of the operating system is the most important issue because of its huge maintenance cost, especially in a deep sea application. In this paper, we propose a new redundant architectural design for the hydraulic control system of an underwater construction robot. The proposed architecture consists of dual independent modular redundancy management systems linked with a commercial profibus network. A cold standby redundancy management system consisting of a preprocessing switch circuit is applied to the signal network, and a hot standby redundancy management system is adapted to utilize two main controllers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.