• 대한전기학회논문지:시스템및제어부문D
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• 제53권12호
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• pp.804-810
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• 2004

There are two important things for the general purpose neural network processor. The first is a capability to build various structures of neural network, and the second is to be able to support suitable learning method for that neural network. Some way to process various learning algorithms is required for on-chip learning, because the more neural network types are to be handled, the more learning methods need to be built into. In this paper, an improved hardware structure is proposed to compute various kinds of learning algorithms flexibly. The hardware structure is based on the existing modular neural network structure. It doesn't need to add a new circuit or a new program for the learning process. It is shown that rearrangements of the existing processing elements can produce several neural network learning modules. The performance and utilization of this module are analyzed by comparing with other neural network chips.

• ETRI Journal
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• 제39권5호
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2005년도 춘계학술대회 논문집
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• pp.377-382
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• 2005

This paper describes the design of micro machine tools system for mechanical machining of micro/meso scale mechanical parts. The micro machining systems such as $\mu-Late$, $\mu-milling/drilling$ machine and $\mu-grinding$ machine are the basic elements constructing $\mu-factory$ which gains more attention recently because of increasing needs of mico and nano-parts in various industrial and medical area. A miniaturized 3-axis milling machine with VCM stage and air spindle and palm-top size micro-late are designed, and air bearing stage and stepwise linear motion system with PZT are studied for motion system. The micro cutting characteristics are investigated experimentally, and reconfigurable machine structures are also considered.

• Current Optics and Photonics
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• 제5권2호
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• pp.134-140
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• 2021

In this paper, I introduce a novel design method of a high performance nanophotonic beam deflector providing broadband operation, large active tunability, and signal efficiency, simultaneously. By combining thermo-optically tunable vanadium dioxide nano-ridges and a metallic mirror, reconfigurable local optical phase of reflected diffraction beams can be engineered in a desired manner over broad bandwidth. The active metagrating deflectors are systematically designed for tunable deflection of reflection beams according to the thermal phase-change of vanadium dioxide nano-ridges. Moreover, by multiplexing the phase-change supercells, a robust design of actively tunable beam splitter is also verified numerically. It is expected that the proposed intuitive and simple design method would contribute to development of next-generation optical interconnects and spatial light modulators with high performances. The author also envisions that this study would be fruitful for modern holographic displays and three-dimensional depth sensing technologies.

• 정보처리학회논문지C
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• 제17C권1호
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• pp.89-98
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• 2010

GEM(Globally Executable MHP) 기반의 MHP(Multimedia Home Platform), OCAP(OpenCable Application Platform), ACAP(Advanced Common Application Platform) 등은 현재 디지털 방송의 대표적인 미들웨어이다. 이러한 미들웨어에 사용된 MPEG-2와 DSM-CC(Digital Storage Media-Command and Control) 프로토콜 표준은 많은 부분이 유사하다는 특징을 가지고 있지만 각 DTV 미들웨어가 필요로 하는 정보와 데이터 구조가 조금씩 차이가 있다. 이는 결과적으로 미들웨어간의 비호환성을 야기한다. 본 논문에서는 다양한 미들웨어 표준을 모두 지원할 수 있는 통합 DTV 미들웨어를 개발하기 위한 노력의 일환으로써, 재구성이 가능한 범용 DSM-CC 아키텍처를 제안한다. 첫째, 모든 GEM 기반의 미들웨어가 공통적으로 필요로 하는 DSM-CC 컴포넌트를 정의하였다. 둘째, 각 미들웨어가 필요로 하는 정보와 데이터 구조를 XML 형태로 정의하여 별도의 수정 없이 정적, 혹은 동적으로 특정 미들웨어에 맞추어 적용할 수 있도록 하였다. 또한, 셋탑박스의 전체적인 성능과 연관성이 높은 어플리케이션 응답시간과 DSM-CC 모듈의 사용빈도를 향상시키기 위해 사용자의 선호도를 고려한 캐시 관리 전략을 제안하고, 제안된 캐시 관리 전략이 응답시간을 줄이는데 효과적임을 실험을 통해서 확인하였다.

• Smart Structures and Systems
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• 제5권1호
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• pp.43-54
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• 2009

This study introduces a novel approach for locating damage in a structure using wireless sensor system with local level computational capability to alleviate data traffic load on the centralized computation. Smart wireless sensor systems, capable of iterative damage-searching, mimic an optimization process in a decentralized way. The proposed algorithm tries to detect damage in a structure by monitoring abnormal increases in strain measurements from a group of wireless sensors. Initially, this clustering technique provides a reasonably effective sensor placement within a structure. Sensor clustering also assigns a certain number of master sensors in each cluster so that they can constantly monitor the structural health of a structure. By adopting a voting system, a group of wireless sensors iteratively forages for a damage location as they can be activated as needed. Since all of the damage searching process occurs within a small group of wireless sensors, no global control or data traffic to a central system is required. Numerical simulation demonstrates that the newly developed searching algorithm implemented on wireless sensors successfully localizes stiffness damage in a plate through the local level reconfigurable function of smart sensors.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}