• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.61-65
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• 2010

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.169-181
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• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• 전자공학회논문지D
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• 제34D권8호
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• pp.35-40
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• 1997

To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.