• Journal of Information Processing Systems
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• v.7 no.4
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• pp.613-626
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• 2011

In this paper, we focus on the pinwheel task model with a variable voltage processor with d discrete voltage/speed levels. We propose an intra-task DVS algorithm, which constructs a minimum energy schedule for k tasks in O(d+k log k) time We also give an inter-task DVS algorithm with O(d+n log n) time, where n denotes the number of jobs. Previous approaches solve this problem by generating a canonical schedule beforehand and adjusting the tasks' speed in O(dn log n) or O($n^3$) time. However, the length of a canonical schedule depends on the hyper period of those task periods and is of exponential length in general. In our approach, the tasks with arbitrary periods are first transformed into harmonic periods and then profile their key features. Afterward, an optimal discrete voltage schedule can be computed directly from those features.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.6
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• pp.506-513
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• 2002

Distributed control systems(DCS) using fieldbus such as CAN have been applied to process systems but it is very difficult to design the DCS while guaranteeing the given end-to-end constraints such as precedence constraints, time constraints, and periods and priorities of tasks and messages. This paper presents a scheduling method to guarantee the given end-to-end constraints. The presented scheduling method is the integrated one considering both tasks executed in each node and messages transmitted via the network and is designed to be applied to a general DCS that has multiple loops with several types of constraints, where each loop consists of sensor nodes with multiple sensors, actuator nodes with multiple actuators and controller nodes with multiple tasks. An assignment method of the optimal period of each loop and a heuristic assignment rule of each message's priority are proposed and the integrated scheduling method is developed based on them.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.6
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• pp.173-178
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• 2014

By exploiting parallel processing, the proposed scheduling scheme enhances energy saving capability of multicore processors for real-time tasks while satisfying deadline and fault tolerance constraints. The scheme searches for a near minimum-energy schedule within a polynomial time, because finding the minimum-energy schedule on multicore processors is a NP-hard problem. The scheme consumes manifestly less energy than the state-of-the-arts method even with low parallel processing speedup as well as with high parallel processing speedup, and saves the energy consumption up to 86%.

• Journal of the Korea Society of Computer and Information
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• v.29 no.1
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• pp.1-9
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• 2024

This paper proposes an integration of the ED-H scheduling algorithm, known for optimal real-time scheduling, with the LoRaEnergySim simulator. This integration facilitates the simulation of interactions between real-time scheduling algorithms for tasks with time constraints in Class-A LoRaWAN Class-A devices using a super-capacitor-based energy harvesting system. The time and energy characteristics of LoRaWAN status and state transitions are extracted in a log format, and the task model is structured to suit the time-slot-based ED-H scheduling algorithm. The algorithm is extended to perform tasks while satisfying time constraints based on CPU executions. To evaluate the proposed approach, the ED-H scheduling algorithm is executed on a set of tasks with varying time and energy characteristics and CPU occupancy rates ranging from 10% to 90%, under the same conditions as the LoRaEnergySim simulation results for packet transmission and reception. The experimental results confirmed the applicability of co-simulation by demonstrating that tasks are prioritized based on urgency without depleting the supercapacitor's energy to satisfy time constraints, depending on the scheduling algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.9
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• pp.1492-1512
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• 2011

Due to multiple hops, mobility and time-varying channel, supporting delay sensitive real-time traffic in wireless local area network-based (WLAN) mesh networks is a challenging task. In particular for real-time traffic subject to medium access control (MAC) layer control overhead, such as preamble, carrier sense waiting time and the random backoff period, the performance of real-time flows will be degraded greatly. In order to support real-time traffic, an efficient adaptive packet scheduling (APS) scheme is proposed, which aims to improve the system performance by guaranteeing inter-class, intra-class service differentiation and adaptively adjusting the packet length. APS classifies incoming packets by the IEEE 802.11e access class and then queued into a suitable buffer queue. APS employs strict priority service discipline for resource allocation among different service classes to achieve inter-class fairness. By estimating the received signal to interference plus noise ratio (SINR) per bit and current link condition, APS is able to calculate the optimized packet length with bi-dimensional markov MAC model to improve system performance. To achieve the fairness of intra-class, APS also takes maximum tolerable packet delay, transmission requests, and average allocation transmission into consideration to allocate transmission opportunity to the corresponding traffic. Detailed simulation results and comparison with IEEE 802.11e enhanced distributed channel access (EDCA) scheme show that the proposed APS scheme is able to effectively provide inter-class and intra-class differentiate services and improve QoS for real-time traffic in terms of throughput, end-to-end delay, packet loss rate and fairness.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.273-283
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• 2008

Many embedded real-time systems have adopted processors supported with dynamic voltage scaling(DVS) recently. Power is one of the important metrics for optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor supported with DVS. In this paper, we propose heuristic algorithms to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. The previous algorithm has a following constraint : given the tasks are ordered in a nondecreasing order of their relative deadline, the task slowdown factors computed are in a nonincreasing order. In this paper, we relax the constraint and propose heuristic algorithms which have the same time complexity that previous algorithm has and can save more energy. Experimental results show that the proposed algorithms are energy efficient.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.93-98
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• 2011

While the use of battery-powered embedded systems has been rapidly increasing, the current level of battery technology has not kept up with the drastic increase in power consumption by the system. In order to prolong system usage time, the battery size needs to be increased. The amounts of power consumption by embedded systems are determined by their hardware configuration and software for manipulating hardware resources. In spite of that, the hardware provides features for lowering power consumption, if those cannot be utilized efficiently by software including operating system, reduction in power consumption is not optimized. In this paper, we propose a BET(Break Even Time)-based scheduling method using task partition to reduce power consumption of multimedia applications in a mobile embedded system environment.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.289-293
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• 2000

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.25-33
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• 2014

This paper proposes a power-efficient scheduling scheme that stochastically minimizes the power consumption of real-time tasks while meeting their deadlines on multicore processors. In the proposed scheme, uncertain computation amounts of given tasks are translated into probabilistic computation amounts based on their past completion amounts, and the mean power consumption of the translated probabilistic computation amounts is minimized with a finite set of discrete clock frequencies. Also, when system load is low, the proposed scheme activates a part of all available cores with unused cores powered off, considering the leakage power consumption of cores. Evaluation shows that the scheme saves up to 69% power consumption of the previous method.