• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.347-353
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• 2017

We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.184-188
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• 2014

There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability ($V_{WL,OPT}=1.055V$) as well as to lower the minimum operating voltage for the read and write operations simultaneously ($V_{MIN,READ}=0.58V$, $V_{MIN,WRITE}=0.82V$ for supply voltage $(V_{DD})=1.1V$).

• 한국정보통신학회논문지
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• 제16권7호
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• pp.1455-1462
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• 2012

본 논문에서는 BCD 공정 기반으로 PMIC용 고신뢰성 24비트 듀얼 포트(dual port) eFuse OTP 메모리를 설계하였다. 제안된 dynamic pseudo NMOS 로직회로를 이용한 프로그램 데이터 비교회로는 program-verify-read 모드에서 프로그램 데이터와 read 데이터를 비교하여 PFb(pass fail bar) 핀으로 비교 결과를 출력한다. 그래서 한 개의 PFb 핀만 테스트하므로 eFuse OTP 메모리가 정상적으로 프로그램 되었는지를 확인할 수 있다. 그리고 program-verify-read 모드를 이용하여 프로그램된 eFuse 저항의 변동을 고려한 가변 풀-업 부하(variable pull-up load)를 갖는 센싱 마진 테스트 회로를 설계하였다. Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 eFuse OTP 메모리의 레이아웃 면적은 $289.9{\mu}m{\times}163.65{\mu}m$($=0.0475mm^2$)이다.

• 한국정보전자통신기술학회논문지
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• 제12권3호
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• pp.312-320
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• 2019

본 논문에서는 110nm eFlash 셀을 사용한 512Kb eFlash IP를 설계하였다. eFlash 셀의 프로그램, 지우기와 읽기 동작을 만족시키는 row 구동회로(CG/SL 구동회로), write BL 구동회로( write BL 스위치 회로와 PBL 스위치 선택 회로), read BL 스위치 회로와 read BL S/A 회로와 같은 eFlash 코어회로(Core circuit)를 제안하였다. 그리고 프로그램 모드에서 9.5V와 erase 모드에서 11.5V의 VPP(Boosted Voltage) 전압을 공급하는 VPP 전압 발생기회로는 기존의 단위 전하펌프 회로로 cross-coupled NMOS 트랜지스터를 사용하는 대신 body 전압을 ground에 연결된 12V NMOS 소자인 NMOS 프리차징 트랜지스터의 게이트 노드 전압을 부스팅하는 회로를 새롭게 제안하여 VPP 단위 전하펌프의 프리차징 노드를 정상적으로 VIN(Input Voltage) 전압으로 프리차징 시켜서 VPP 전하펌프 회로의 펌핑 전류를 증가시켰다. 펌핑 커패시터로는 PMOS 펌핑 커패시터에 비해 펌핑전류가 크고 레이아웃 면적이 작은 12V native NMOS 펌핑 커패시터를 사용하였다. 한편 110nm eFlash 공정을 기반으로 설계된 512Kb eFlash 메모리 IP의 레이아웃 면적은 $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$이다.

• 한국전자통신학회논문지
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• 제18권4호
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• pp.625-640
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• 2023

본 논문에서는 IoT 응용에서 사용되는 인덕티브한 센서의 인덕턴스를 측정할 수 있는 회로를 제안하였다. RL 저역 통과 필터 회로, 비교기, 전류 제어 스위치, 커패시터의 특성을 이용하여 회로를 구성하였으며, RL 저역 통과 필터 회로의 출력 전압이 기준 전압보다 큰 duration time을 통해 1nH-1H 범위 내의 인덕턴스 값을 도출 할 수 있다.

• 대한전자공학회논문지SD
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• 제47권12호
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• pp.31-38
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• 2010

본 논문에서는 QVGA급 LCD Driver IC(LDI)의 그래픽 메모리를 설계한다. 저면적을 위해 pseudo-SRAM 구조로 설계하고, 센싱 특성 개선과 line-read 동작 시 구동력 향상을 위해 bit line을 분할한 cell array 구조를 적용한다. 또한, C-gate를 이용한 저면적의 충돌방지 회로를 사용하여 그래픽 메모리의 line-read/self-refresh 동작과 기존의 write/read 동작 상호간의 충돌을 효과적으로 제어하는 방식을 제안한다. QVGA급 LDI의 그래픽 메모리는 $0.18{\mu}m$ CMOS공정을 이용하여 트랜지스터 레벨로 설계하고 회로 시뮬레이션을 통해 그래픽 메모리의 write, read, line-read, self-refresh 등의 기본 동작을 확인하고, 제안된 충돌방지 블록에 대한 동작을 확인하였다. 개선된 cell array를 통해 bit/bitb line 전압차 ${\Delta}V$는 약 15% 증가하고, bit/bitb line의 charge sharing time $T_{CHGSH}$는 약 30% 감소하여 센싱 특성이 향상되었으며, line-read 동작 시 발생하는 전류는 약 40% 크게 감소되었다.

• 한국전기전자재료학회논문지
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• 제13권4호
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• pp.273-279
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• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• Progress in Superconductivity
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• 제1권2호
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• pp.105-109
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• 2000

We have designed and fabricated a single-flux-quantum(SFQ) four-stage shift register using YBCO bicrystal Josephson junctions, and tested its operations using a digital measurement set-up. The circuit consists of 4 shift register stages and a read SQUID placed next to each side of the shift register. Each SQUID was inductively coupled to the nearby shift register stage. The major obstacle in testing the circuits was the interference between the two read SQUIDs, and we could get over the problem by determining the correct operation points of the SQUID from the simultaneously measured modulation curves. Loaded data ('1' or '0') were successfully shifted from a stage to the next by a controlled current pulse injected to the bias lines located between the stages, and the corresponding correct data shifts were observed with the two read SQUIDs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.300-308
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• 2010

This paper describes the development of a low-power electrocardiogram (ECG) touch sensor intended for the use with two dry metal electrodes. An equivalent ECG extraction circuit model encountered in a ground-free two-electrode configuration is investigated for an optimal sensor read-out circuit design criteria. From the equivalent circuit model, (1) maximum sensor resolution is derived based on the electrode's background thermal noise, which originates from high electrode-skin contact impedance, together with the input referred noise of instrumentation amplifier (IA), (2) 60 Hz electrostatic coupling from mains and motion artifact are also considered to determine minimum requirement of common mode rejection ratio (CMRR) and input impedance of IA. A dedicated ECG read-out front end incorporating chopping scheme is introduced to provide an input referred circuit noise of 1.3 ${\mu}V_{rms}$ over 0.5 Hz ~ 200 Hz, CMRR of IA > 100 dB, sensor resolution of 7 bits, and dissipating only 36 ${\mu}W$. Together with 8 bits synchronous successive approximation register (SAR) ADC, the sensor IC chip is implemented in 0.18 ${\mu}m$ CMOS technology and integrated on a 5 cm $\times$ 8 cm PCB with two copper patterned electrodes. With the help of proposed touch sensor, ECG signal containing QRS complex and P, T waves are successfully extracted by simply touching the electrodes with two thumbs.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2013년도 춘계학술발표대회
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• pp.21-23
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• 2013

Static Random Access Memory (SRAM) using CMOS technology has many advantages. It does not need to refresh every certain time, as a result, the speed of SRAM is faster than Dynamic Random Access Memory (DRAM). This is the reason why SRAM is widely used in almost processors and system on chips (SoC) which require high processing speed. Two basic operations of SRAM are read and write. We consider two basic factors, including the accuracy of read and write operations and the speed of these operations. In our paper, we propose the read and write assist circuits for SRAM. By adding a power control circuit in SRAM, the write operation performed successfully with low error ratio. Moreover, the value in memory cells can be read correctly using the proposed pre-charge method.