• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.21.2-21.2
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• 2011

$Fe_3O_4$ having half metallic property is one of the efficient spin filtering materials which are widely used in spintronic research field and ZnO is wide band gap semiconductor which can be used by tunnel barrier or semiconductor channel in spin MOSFET. We investigated the magnetic and the electric properties of $Fe_3O_4$/ZnO multilayer fabricated on c-$Al_2O_3$ substrate by pulsed laser deposition (PLD). For multilayer films, PLD was performed at variable temperatures such as $200{\sim}750^{\circ}C$ and at target distance from 40 to 80 mm, KrF eximer laser of 1.5 $J/cm^2$ and a reputation rate of 2Hz. $Fe_3O_4$/ZnO multilayers were deposited at $4{\times}10^{-6}$ Torr. After fabricating $Fe_3O_4$/ZnO multilayers, $Fe_3O_4$/ZnO multilayers were treated by RTA(Rapid Thermal Annealing) at various temperature to change magnetic phase. The magnetism of the multilayer is changed by thickness of the ZnO tunnel barrier. Magnetic phase of FexOy showed a very small magnetism due to $Fe_2O_3$ ${\alpha}$-phase, but large magnetism from $Fe_3O_4$ or $Fe_2O_3$ ${\gamma}$-phase was observed. In the present study, effect of the ZnO thickness on the MR (magnetoresistance) ratio was investigated in detail.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.45-49
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• 2014

In this study, we grew non-polar ZnO nanostructure on (1-102) R-plane sapphire substrates. As for growth method of ZnO, we used hydrothermal synthesis which is known to have the advantages of low cost and easy process. For growth of non-polar, the deposited AZO seed buffer layer with of 80 nm on R-plane sapphire by radio frequency magnetron sputter was annealed by RTA(rapid thermal annealing) in the argon atmosphere. After that, we grew ZnO nanostructure on AZO seed layer by the added hexamethylenetramine (HMT) solution and sodium citrate at $90^{\circ}C$. With two types of additives into solution, we investigated the structures and shapes of ZnO nanorods. Also, we investigate the possibility of formation of 2D non-polar ZnO layer by changing the ratio of two additives. As a result, we could get the non-polar A-plane ZnO layer with well optimized additives' concentrations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.998-1001
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• 2004

ZnO, $SnO_2$ 타겟 각각의 RF 파워를 50 W, 38 W로 고정시킨 후 combinatorial RF magnetron sputtering법을 사용하여 기판 위치에 따라서 조성 구배를 주어 여러 가지 조성의 Zn-Sn-O(ZTO) 박막을 제작하였다. 시편의 열처리에 따른 물성 변화를 분석하기 위해 Rapid Thermal Annealer(RTA)을 이용하여 450, $650{^\circ}C$의 온도 및 $10^{-2}$ Ton의 진공 분위기에서 각각 1 시간 동안 열처리하였다. XRD 분석 결과 상온에서 제작된 ZTO 박막은 Sn 18 at%의 조성을 갖는 시편을 제외하고 모두 비정질상으로 나타났다. $450^{\circ}C$에서 열처리 후 구조적인 변화는 보이지 않았으나, 캐리어 농도와 이동도는 증가하였으며 Sn 54 at%의 조성에서 최고 $25.4cm^2/Vsec$의 전자 이동도를 나타내었다. $26{\leq}Sn$ $at%{\leq}65$의 조성 범위를 갖는 박막은 가시광 영역에서 80 % 이상의 투과도를 가졌으며 $650^{\circ}C$에서 결정화가 되면서 투과도가 증가하였다.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.61-67
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• 2003

The interfacial reaction between ultra-small 58Bi-42Sn solder and Au/Ni/Ti under bump metallurgy (UBM) for ultra-fine flip chip application was investigated. The ultra-small 58Bi-42Sn solder bump, about $46{\mu}m$ in diameter, was fabricated by using the lift-off method and reflowed using the rapid thermal annealing (RTA) system. The intermetallic compounds were characterized using a secondary electron microscopy (SEM), an energy dispersive spectroscopy (EDS), and an x-ray diffractometer (XRD). The faceted and polygonal intermetallic compounds were found in the Bi-Sn solder bumps on $Au(0.1{\mu}m)/Ni/Ti$ UBM and they were indentified as $(Au_xBi_yNi_{1-x-y})Sn_2$ Phase. The intermetallic compounds grown from the $Au(0.1{\mu}m)/Ni/Ti$ UBMinterface were dispersed in the solder bump.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.186-189
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• 2003

The role of excess Pb about the crystallization behavior and electrical properties in b(Zr$\sub$0.52/Ti$\sub$0.48/)O3(PZT) thin films has not been precisely defined. In this work, the effect of excess Pb content on the ferroelectric properties of these films was investigated. To analyze the effect, PZT films containing various amounts of excess Pb were Prepared. PZT thin films were deposited on the Pt/Ti bottom electrode by rf magnetron sputtering method and then they were crystallized by rapid thermal annealing (RTA). The experiment showed that all PZT films indicated perovskite polycrystalline structure with preferred orientation (111) and no pyrochlore phase was observed. As higher excess Pb was included, the films showed that value of leakage current shift from 2.03${\times}$10$\^$-6/ to 6.63 ${\times}$ 10$\^$-8/A/cm$^2$ at 100kV/cm, and value of remanent polarization shift from 8.587 ${\mu}$C /cm$^2$ to 4.256 ${\mu}$C/ cm$^2$. Electrical properties of PZT thin film affected by Pb excess content of target were explained to be caused of defect among space charges and defect grain boundaries.

• Korean Journal of Materials Research
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• v.19 no.4
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• pp.179-185
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• 2009

We fabricated thermally evaporated 30 nm-Ni/(20 nm or 60 nm)a-Si:H/Si films to investigate the energy-saving property of silicides formed by rapid thermal annealing (RTA) at temperatures of $350^{\circ}C$, $450^{\circ}C$, $550^{\circ}C$, and $600^{\circ}C$ for 40 seconds. A transmission electron microscope (TEM) and a high resolution X-ray diffractometer (HRXRD) were used to determine the cross-sectional microstructure and phase changes. A UVVIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were employed for near-IR and middle-IR absorbance. Through TEM and HRXRD analysis, for the nickel silicide formed at low temperatures below $450^{\circ}C$, we confirmed columnar-shaped structures with thicknesses of $20{\sim}30\;nm$ that had ${\delta}-Ni^2Si$ phases. Regarding the nickel silicide formed at high temperatures above $550^{\circ}C$, we confirmed that the nickel silicide had more than 50 nm-thick columnar-shaped structures with a $Ni_{31}Si_{12}$ phase. Through UV-VIS-NIR analysis, nickel silicide showed almost the same absorbance in the near IR region as well as ITO. However, in the middle IR region, the nickel silicides with low temperature showed similar absorbance to those from high temperature silicidation.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.67-67
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• 2000

CeO2는 cubic 구조의 일종인 CaR2 구조를 가지고 있으며 격자상수가 Si의 격장상수와 매우 비슷하여 Si 기판위에 에피텍셜하게 성장할 수 있는 가능성이 매우 크다. 따라서 SOI(silicon-on-insulator)구조의 실현을 위하여 Si 기판위에 CeO2 박막을 에피텍셜하게 성장시키려는 많은 노력이 있어왔다. 또한 metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이의 완충층으로 사용된다. 이러한 CeO2의 응용을 위해서는 Si 기판 위에 성장된 CeO2 박막의 방위성 및 CeO2/Si 구조의 전기적 특성을 알아보는 것이 매우 중요하다. 본 연구에서는 Si(100) 기판위에 CeO2(200)방향으로 성장하는 박막과 EcO2(111) 방향으로 성장하는 박막을 rf magnetron sputtering 방법으로 증착하여 각각의 구조적, 전기적 특성을 분석하였다. RCA 방법으로 세정한 P-type Si(100)기판위에 Ce target과 O2를 사용하여 CeO2(200) 및 CeO2(111)박막을 증착하였다. 증착후 RTA(rapid thermal annealing)방법으로 95$0^{\circ}C$, O2 분위기에서 5분간 열처리를 하였다 이렇게 제작된 CeO2 박막의 구조적 특성을 XRD(x-ray diffraction)방법으로 분석하였고, Al/CeO2/Si의 MIS(metal-insulator-semiconductor)구조를 제작하여 C-V (capacitance-voltage), I-V (current-voltage) 특성을 분석하였으며 TEM(transmission electron microscopy)으로 증착된 CeO2막과 Si 기판과의 계면 특성을 연구하였다. C-V특성에 있어서 CeO2(111)/Si은 CeO2(111)의 두께가 증가함에 따라 hysteresis windows가 증가한 방면 CeO2(200)/Si은 hysteresis windows가 아주 작을뿐만 아니라 CeO2(200)의 두께가 증가하더라도 hysteresis windos가 증가하지 않았다. CeO2(111)/Si과 CeO2(200)/Si의 C-V 특성의 차이는 CeO2(111)과 CeO2(200)이 Si 기판에 의해 받은 stress의 차이와 이에 따른 defect형성의 차이에 의한 것으로 사료된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.301-301
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• 2010

2010년경 2.5G APD 시장은 3, 000억원 규모로 증가하는데 이는 FTTH 망의 확산에 힘입은 바 크다. 이와 같이 중요한 APD 소자는 현재 광통신 부품시장을 석권해 가고 있는 대만, 중국 업체들은 제조기술을 갖고 있지 않고 주로 미국-일본 기술에 의존하고 있기 때문에 Niche market으로 중요한 부품이라 할 수 있다. APD의 증폭은 높은 전기장에 의해 얻어지는데, 이 때문에 메사형 구조로는 신뢰성을 확보하기 어렵게 되고 따라서 평면형(Planar) 구조로 설계-제작하게 된다. APD 소자는 증폭층의 너비에 의해 APD의 이득-대역폭이 정해지므로 증폭층 폭을 정확하게 조절하는 것은 매우 중요하다. 증폭층의 폭은 에피 성장과 같은 높은 정밀성을 갖는 장비에 의해 조절하는 것이 아니라, Planar 구조의 특성상 Zn-확산에 의해 조절하게 된다. 대부분의 경우 Zn-확산은 Zn 또는 $Zn_3P_2$를 증착하여 drive-in 시키는 방법을 사용하는데, 이 경우 Zn가 interstitial site를 치고 들어감으로 인해 캐리어 농도가 $2{\times}10^{17}\;cm^{-3}$ 정도로 낮게 형성된다. 따라서 높은 인가 바이어스에서 p-side로 공핍층이 전개되기 때문에 증폭층의 폭을 조절하기가 매우 어렵다. 이 현상은 APD 제작에 있어서 수율과 관련이 깊다. 따라서 APD의 증폭층 폭을 tight하게 조절하기 위해서는 p-type 캐리어 농도를 높일 수 있는 gas-phase 확산 방식의 개발이 필요하다. 이 방식에는 Ampoule과 같은 closed tube 방식과 확산로와 같이 Gas를 지속적으로 흘려주면서 확산시키는 open-tube 방식이 있다. Ampoule 방식은 캐리어 농도 측면에서는 가장 좋은 방식이나, Ampoule의 size 및 온도 균일성 등으로 인해 생산성에 문제가 있다. 따라서 open-tube 방식의 확산기술개발은 매우 중요하다 할 수 있다. 본 연구에는 rapid thermal annealing (RTA) 방법에 의한 $Zn_3P_2$ 고체의 확산 방식과 DEZn MO source에 의한 Gas 확산 방식을 바탕으로 InP로의 확산된 Zn원자와 doping의 분포를 비교하였다. 실험결과, Gas 확산방식의 경우 Zn원자가 더욱 더 깊게 확산이 되었으며, 확산된 원자의 대부분이 도펀트로 작용함을 확인할 수 있었다.

• Korean Journal of Materials Research
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• v.2 no.5
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• pp.375-382
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• 1992

Molybdenum silicide films have been prepared by sputtering from a single composite MoS$i_2$ source on both P, B$F_2$respectively implanted (5${\times}10^{15}ions/cm^2$ single crystal and P implanted (5${\times}10^{15}ions/cm^2$) polycrystalline silicon substrates followed by rapid thermal annealing in the ambient of argon. The heat treatment temperatures have been varied in the range of 600-l20$0^{\circ}C$ for 20 seconds. The properties of Mo-silicide and the diffusion behaviors of dopant after the heat treatment are investigated using X-ray diffraction, scanning electron microscopy(SEM) , secondary ions mass spectrometry(SIMS), four-point probe and $\alpha-step.$ Annealing at 80$0^{\circ}C$ or higher resulted in conversion of the amorphous phase into predominantly MoS$i_2$and a lower sheet resistance. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into molybdenum silicide layers during annealing.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.