• 전자공학회논문지A
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• 제31A권9호
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• 센서학회지
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• 제27권1호
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• pp.40-46
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• 2018

In this paper, we focus on optimization of a boron ($^{11}B$)-implanted n type Si epi substrate for obtaining near-zero temperature coefficient of resistance (TCR) at temperature range from 25 to $125^{\circ}C$. The $^{11}B$-implantation on the N type-Si epi substrate formed isolation from the rest of the N-type Si by the depletion region of a PN junction. The TCR increased as the temperature of rapid thermal anneal (RTA) was increased at the temperature range from $900^{\circ}C$ to $1000^{\circ}C$ for the $p^+$ contact with implantation at dose of $1E16/cm^2$, but sheet resistance of this film was decreased. After the optimization of anneal process condition, the TCR of $1126.7{\pm}30.3$ (ppm/K) was obtained for the $p^-$ resistor-COB package chips contained $p^+$ contact with the implantation of $5E14/cm^2$. This shows the potential of the $^{11}B$-implanted n type Si epi substrate as a resistor for pressure sensor in thermal stable environment applications..

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.542-545
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• 1987

THE ELECTRICAL CHARACTERISTICS Of RAPID THERMAL OXIDES AND NITRIDED OXIDES HAVE BEEN INVESTIGATED. R.T.OXIDE FILMS HAVE BEEN PREPARED BY ONLY R.T. OXIDATION OR R.T.OXIDATION AND SUBSEQUENT R.T.ANNEAL. NITRIDED OXIDE FILMS HAVE BEEN PREPARED BY R.T.OXIDATION AND SUBSEQUENT R.T.NITRIDATION.AND CONVENTIONAL OXIDES ALSO HAVE BEEN PREPARED TO COMPARE WITH R.T.P OXIDES. R.T.ANNEALED OXIDES SHOW EXCELLENT BREAKDOWN FIELD. LEAKAGE CURRENT AND TDDB CHARACTERISTICS. ALSO, CAPACITANCE Of R.T NITRIDED OXIDES ARE SUPERIOR BY 10% TO CONVENTIONAL OXIDES, BUT TDDB CHARACTERISTIC ARE POORER THAN OXIDE FILMS.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.375-381
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• 2001

디바이스의 크기가 0.25㎛이하로 축소됨에 따라 DRAM(Dynamic Random Access Memory) 제조업체들은 칩 크기를 줄이고 지역적인 배선으로 사용하기 위해서 기존의 텅스텐-폴리사이드 비트-선에서 텅스텐 비트-선으로 대체하고 있다. 본 논문에서는 다양한 RTP 온도와 추가 이온주입을 사용하여 낮은 저항을 갖는 텅스텐 비트-선 제조 공정에 대해 다루었다. 그 결과 텅스텐 비트선 저항에 중요한 메계변수는 RTP Anneal 온도와 BF₂ 이온 주입 도펀트임을 알 수 있었다. 이러한 텅스텐 비트-선 공정은 고밀도 칩 구현에 중요한 기술이 된다.

• 대한전기학회논문지
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• 제45권2호
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• pp.242-248
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• 1996

The properties of TiN/TiSi$_{2}$ bilayer formed by a rapid thermal annealing is investigated when thin SiO$_{2}$ film exists at the Ti-Si interface. The competitive reaction for the TiN/TiSi_2 bilayer occurs above 600 .deg. C. The thickness of the TiSi$_{2}$ layer decreases with increasing SiO$_{2}$ film thickness and also decreases with increasing anneal temperture When the competitive reaction for the TiN/TiSi$_{2}$ bilayer is occured by rapid thermal annealing, the composition of TiN layer represents TiN$_{x}$O$_{y}$ due to the SiO$_{2}$ layer at the Ti-Si interface but the structures of the TiN and TiSi$_{2}$ layers were not changed.d.d.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2009년도 춘계학술발표대회 논문집
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• pp.230-234
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• 2009

It is significant technique to increase competitiveness that solar cells have a high energy conversion efficiency and cost effectiveness. When making high efficiency crystalline Si solar cells, evaporated Ti/Pd/Ag contact system is widely used in order to reduce the electrical resistance of the contact fingers. However, the evaporation process is no applicable to mass production because high vacuum is needed. Furthermore, those metals are too expensive to be applied for terrestrial applications. Ni/Cu/Ag contact system of silicon solar cells offers a relatively inexpensive method of making electrical contact. Ni silicide formation is one of the indispensable techniques for Ni/Cu/Ag contact sytem. Ni was electroless plated on the front grid pattern, After Ni electroless plating, the cells were annealed by RTP(Rapid Thermal Process). Ni silicide(NiSi) has certain advantages over Ti silicide($TiSi_2$), lower temperature anneal, one step anneal, low resistivity, low silicon consumption, low film stress, absence of reaction between the annealing ambient. Ni/Cu/Ag metallization scheme is an important process in the direction of cost reduction for solar cells of high efficiency. In this article we shall report an investigation of rapid thermal silicidation of nickel on silngle crystalline silicon wafers in the annealing range of $350-390^{\circ}C$. The samples annealed at temperatures from 350 to $390^{\circ}C$ have been analyzed by SEM(Scanning Electron Microscopy).

• 한국진공학회지
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• 제17권2호
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• pp.156-159
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• 2008

Pseudo-MOSFET 방법을 이용하여 Ge농도에 따른 SiGe-on-Insulator(SGOI) 기판의 특성을 평가하였다. SGOI 기판은 compressive-SiGe / Relaxed-Si / Buried oxide / Si-substrate 구조로 SOI 기판 위에 에피택셜 성장법으로 SiGe층을 형성하였으며 compressive SiGe층의 Ge 농도는 각각 16.2％, 29.7％, 34.3％, 56.5％ 이다. 실험결과 Ge 농도가 증가함에 따라 누설전류가 증가하는 특성을 보였으며 threshold voltage는 nMOSFET의 경우 3V에서 7V로 이동하였으며 pMOSFET의 경우도 -7 V에서 -6 V로 이동하는 특성을 보였다. 급속 열처리 공정 (rapid thermal anneal) 후에 매몰 산화층과 기판 계면간의 스트레스에 의한 포획준위가 발생하여 소자특성이 열화되었지만, $H_2/N_2$ 분위기에서 후속 열처리 공정 (post RTA anneal) 을 통하여 계면 간의 포획준위를 감소시켜 SGOI Pseudo-MOSFET의 전기적 특성이 개선되었다.

• 대한전기학회논문지
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• 제41권6호
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• pp.633-639
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• 1992

The physical and electrical properties of TiN/TiSiS12T contact barrier were studied. The TiN/TiSiS12T system was formed by rapid thermal anneal in NS12T ambient after the Ti film was deposited on silicon substrate. The Ti film reacts with NS12T gas to make a TiN layer at the surface and reacts with silicon to make a TiSiS12T layer at the interface respectively. It was found that the formation of TiN/TiSiS12T system depends on RTA temperature. In this experiment, competitive reaction for TiN/TiSiS12T system occured above $600^{\circ}C$. Ti-rich TiNS1xT layer and Ti-rich TiSiS1xT layer were formed at $600^{\circ}C$. stable structure TiN layer and TiSiS1xT layer which has CS149T phase and CS154T phase were formed at $700^{\circ}C$. Both stable TiN layer and CS154T phase TiSiS12T layer were formed at 80$0^{\circ}C$. The thickness of TiN/TiSiS12T system was increased as the thickness of deposited Ti film increased.

• 대한전기학회논문지
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• 제41권8호
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• pp.869-874
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• 1992

The physical and electrical properties of TiN/TiSiS12T bilayer were studied. The TiN/TiSiS12T bilayer was formed by rapid thermal anneal in NHS13T ambient after the Ti film was deposited on silicon substrate. The Ti film reacts with NHS13T gas to make a TiN layer at the surface and reacts with silicon to make a TiSiS12T layer at the interface respectively. It was found that the formation of TiN/TiSiS12T bilayer depends on RTA temperature. In this experiment, competitive reaction for TiN/TiSiS12T bilayer occured above $600^{\circ}C$. Ti-rich TiNS1xT layer and Ti-rich TiSiS1xT layer and Ti-rich TiSiS1xT layer were formed at $600^{\circ}C$. stable structure TiN layer TiSiS12T layer which has CS149T phase and CS154T phase were formed at $700^{\circ}C$. Both stable TiN layer and CS154T phase TiSiS12T layer were formed at 80$0^{\circ}C$. The thickness of TiN/TiSiS12T bilayer was increased as the thickness of deposited Ti film increased.