• IEIE Transactions on Smart Processing and Computing
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• 제4권5호
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• ETRI Journal
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• 제42권5호
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• 한국음향학회지
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• 제14권5호
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• pp.29-35
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• 1995

진동판 변위의 비선형적 운동에 의해 발생하는 스피커의 비선형왜곡은 음질을 열화시킨다. 이러한 비선형왜곡은 저주파 대역의 경우 주로 스피커의 지지부의 강성과 force factor의 비선형 특성에 의해 발생한다. 본 논문에서는 진동판 변위에 따라 변화하는 스피커의 비선형 강성과 비선형 force factor를 2차함수로 모델링하고 각각의 계수를 결정하는 방법에 대해 연구하였다. 진동판에 질량을 부가하여 동작점을 이동시키는 기계적인 방법을 사용하여 강성과 force factor 간의 커플링을 배제하였으며, 여러 동작점에서의 공진주파수를 측정함으로써 비선형 강성의 계수를 추출하였다. 비선형 force factor의 계수는 공진주파수에서 스피커에의 입력전압, 입력전류, 그리고 진동판 변위를 측정하여 얻은 그래프를 curve fitting 함으로써 구하였다.

• 한국표면공학회지
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• 제27권3호
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• pp.158-165
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• 1994

Cu-Cr alloy thin film requires good quality of etching be used for TAB technology. The etched cross sec-tion was clean enough when the etching was performed in 0.1M $FeCl_3$ solution at $50^{\circ}C$. The etching rate was increased with the amount of $KMnO_4$. For enhanced profile of cross section and rate, the spray etchning was found to be superior compared to the immersion etching. A series of experiments were performed to improve the uniformity of the current distribution in electrodeposition onto the substrate with lithographic patterns. Copper was electrodeposited from quiescent-solution, paddle-agitated-solution, and air-bubbled-solution to in-vestigate the effect of the fluid flow. The thickness profile of the specimen measured by profilmetry has the non uniformity at feature scale in quiescent-solution, because of the longitudinal vortex roll caused by the natural convection. However, uniform thickness profile was achieved in paddle-agitated or air bubbled solu-tion.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 한국통신학회논문지
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• 제25권5B호
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• pp.974-984
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• 2000

전압 강하 변환기의 구동 회로를 제안하였다. 구동 회로의 load regulation 특성을 개선하기 위하여 적응 바이어스(adaptive biasing) 개념을 제안하였고 이 개념을 도입한 NMOS 구동 회로를 설계하였다. 적응 바이어스 전류 구동 개념이 적용된 NMOS 구동 회로는 구동단에서의 밀러(Miller) 효과가 없으므로 위상 여유가 크고 안정된 주파수 특성을 보여주고 있다. NMOS 구동단은 같은 구동 전류를 흘려줄 경우 PMOS 구동단에 비해 훨씬 적은 트랜지스터 크기 비로 설계 제작이 가능하므로 칩 면적을 크게 줄일 수 있으며 PMOS 구동단에서의 같은 보상 커패시터나 보상 추로 회로가 없다. 제안된 회로는 0.8 $\mu\textrm{m}$ CMOS 공정 기술을 이용하여 구현되었으며 설계가 간단하고, 대기 전력(quiescent power)이 60 ㎼로 측정되었다. 전체 크기는 150 $\mu\textrm{m}$$\times$ 360 $\mu\textrm{m}$이고 100$\mu\textrm{A}$부터 50 ㎃ 까지의 구동 전류 변화 조건하에서 5.6 ㎷의 load regulation 값을 얻었다.

• 한국통신학회논문지
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• 제27권1C호
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• pp.96-102
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• 2002

전류 테스팅은 전류 테스팅은 CMOS 회로의 합선고장을 효과적으로 검출할 수 있는 기법이다. 그러나 합선고장의 복잡도가 O($n^2$)이고, 또한 전류 테스트 방식이 전압 테스트 방식에 비해서 상대적으로 긴 테스트 시간이 필요하기 때문에 두 합선된 노드가 항상 같은 값을 가지는 노드를 찾아내어 제거하는 효율적인 무해고장 검출기법이 필요하다. 이러한 무해고장은 보다 정확한 고장 검출율을 위해서 ATPG 툴을 이용하여 검출될 수 있어야 한다. 본 논문에서는 효율적인 전류 테스트를 위한 객체 기반의 무해고장 검출기법을 제안한다. ISCAS 벤치마크 회로에 대한 실험을 통해서 제안된 기법이 기존의 다른 방식보다 더 효과적임을 보여주었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.