• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.383-386
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• 2000

There are some variations in quiescent supply current or TTL SSIs. Thus, some variations in quiescent supply current of logic circuits made of TTL SSIs will be generated. The variations make it difficult to apply supply current test methods to tests of TTL circuits. In this paper, in order to examine the applicability to R circuits, fault coverages of a supply current test method for open faults in some ISCAS-85 benchmark circuits are evaluated, Which are made of TTL LS-type SSIs. The experimental results shows that if SSIs are used for implementation having the variation of quiescent supply current within 1%, supply current test methods are applicable for the tests.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.903-906
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• 2003

In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/$\mu$sec and 5$\mu$A, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.530-532
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• 2002

We have developed a low-power, high slew-rate OP-AMP for large size and high resolution TFT-LCDs which have 8${\mu}$A quiescent current with settling time less than 6${\mu}$sec. The proposed OP-AMP contains newly developed the driving circuit of class-AB output stage which can achieve a low quiescent current less than 8${\mu}$A and a slew-rate higher than 3.14V/${\mu}$sec.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.17-18
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• 2000

A low-power source driver for TFT-LCDs has been proposed using the triple charge sharing method that enhances the AC power saving efficiency of the prior charge sharing method. The AC power saving efficiency of the proposed source driver reaches 66.6%. In addition, a novel OP-AMP with low-quiescent current has been developed. The measured quiescent current of the OP-AMP is $5{\mu}A{\sim}7{\mu}A$ at VDD=5V and VSS=0V with load resistance of $2k{\Omega}$ and load capacitance of 300pF.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.513-514
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• 2006

As power supply managements become more important than before, supplying a stable system voltage is becoming more and more critical. In this study we propose to use the advantage of weak inversion region of MOS transistors. Analog system, which uses weak inversion region, could work in low voltage environment and reduce power consumption. The proposed buck-converter in weak inversion region of MOS transistor has been verified by silicon chip.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.4
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• pp.17-26
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• 1997

A enw channel current model of GaAs MeSFET suitagle for applications to microwave CAD has been developed. The current model includes the bias-dependent frequency dispersion effects and its parameters are extracted from the pulsed I-V measurements at several quiescent bias points. The model is verified by applying to the nonlinear circuit designs of power amplifier and MMIC mixer.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.905-908
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• 2005

본 논문에서는 class AB opamp 를 채용한 384kHz differential PWM 신호를 입력으로 하는 2-channel stereo audio amplifier 블록을 공급전압 3.3V 조건에서 SMIC 0.18um thick oxide 기술을 이용하여 설계한다. 여기서 class AB opamp 는 공정 변화에 따른 quiescent current가 변하는 것을 최소화하기 위하여 adaptive load 를 사용하며, 전체적으로는 3 차 Butterworth lowpass filter 와 differential-to-single converter 로 구성된 2 개의 audio amplifier 와 출력전압이 ${\frac{1}{2}}Vdd$ 인 common output 블록으로 구성된다. 이러한 설계를 통하여 32ohm 의 저항 load 를 구동할 수 있는 -60dB THD, 전체 quiescent current 2mA 대인 CMOS class AB stereo audio amplifier 를 구현하였다.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.133-136
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• 2000

A new Op-Amp output buffer is presented for driving large-size LCD panels. The proposed Op-Amp is designed by combining a common source and a common drain amplifier to have a high slew rate and to minimize the quiescent current. The proposed circuits are simulated in a high-voltage 0.6${\mu}{\textrm}{m}$ CMOS process, dissipates only 20${\mu}{\textrm}{m}$ static current, and have 83dB open-loop DC gain and 60$^{\circ}$phase margin.