• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.156-156
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• 2000

Recently, the surface electronic states have attracted much attention since their standing wave patterns created around steps, defects, and adsorbates on noble metal surfaces such as Au(111), Ag(110), and Cu(111) were observed by scanning tunneling microscopy (STM). As a typical example, a striking circular pattern of "Quantum corral" observed by Crommie, Lutz, and Eigler, covers a number of text books of quantum mechanics, demonstrating a wavy nature of electrons. After the discoveries, similar standing waves patterns have been observed on other metal and demiconductor surfaces and even on a side polane of nano-tubes. With an expectation that the surface states could be utilized as one of ideal cases for studying two dimensionakl (sD) electronic system, various properties, such as mean free path / life time of the electronic states, have been characterized based on an analysis of standing wave patterns, . for the 2D electron system, electron density is one of the most importnat parameters which determines the properties on it. One advantage of conventional 2D electron system, such as the ones realized at AlGaAs/GaAs and SiO2/Si interfaces, is their controllability of the electrondensity. It can be changed and controlled by a factor of orders through an application of voltage on the gate electrode. On the other hand, changing the leectron density of the surface-state 2D electron system is not simple. On ewqy to change the electron density of the surface-state 2D electron system is not simple. One way to change the electron density is to deposit other elements on the system. it has been known that Pd(111) surface has unoccupied surface states whose energy level is just above Fermi level. Recently, we found that by depositing Pd on Cu(111) surface, occupied surface states of Cu(111) is lifted up, crossing at Fermi level around 2ML, and approaches to the intrinsic Pd surface states with a increase in thickness. Electron density occupied in the states is thus gradually reduced by Pd deposition. Park et al. also observed a change in Fermi wave number of the surface states of Cu(111) by deposition of Xe layer on it, which suggests another possible way of changing electron density. In this talk, after a brief review of recent progress in a study of standing weaves by STM, I will discuss about how the electron density can be changed and controlled and feasibility of using the surface states for a study of 2D electron system. One of the most important advantage of the surface-state 2D electron system is that one can directly and easily access to the system with a high spatial resolution by STM/AFM.y STM/AFM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Korean Journal of Optics and Photonics
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• v.13 no.6
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• pp.543-547
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• 2002

We have constructed two extended-cavity diode lasers which are phase-locked with a 9.2 GHz frequency offset. We adopted a digital servo circuit for the phase-locking. The relative linewidth of the phase-locked lasers was less than 2 Hz. Using the measured beat spectrum, we found the carrier concentration to be about 93 %. We measured phase noise and relative frequency stability of the lasers. The Allan deviation at the gate time of 20 s was $2.7{\times}10^{-19}$.

• Korean Journal of Optics and Photonics
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• v.17 no.6
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• pp.564-568
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• 2006

Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.11-11
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• 2007

1차원 구조체인 반도체 나노선은 앙자제한효과 (quantum confinement effect) 등을 이용하여 고밀도/고효율의 소자 개발이 기대되고 있다. GaN는 상온에서 3.4 eV의 밴드갭 에너지를 갖는 III-V 족 반도체 재료로써 박막의 경우 광전자 소자로 폭넓게 응용되고 있다. 최근 GaN 나노선의 합성에 성공하면서 발광소자, 고효율의 태양전지, HEMT 등으로의 응용을 위한 많은 연구가 활발히 이루어지고 있다. 하지만, 아직까지 GaN 나노선의 전기적 특성을 제어하는 기술은 확립되지 않고 있다. 본 연구에서는 Vapor solid (VS)법을 이용하여 GaN 나노선을 합성하였으며, GaN 분말과 함께 $Mg_2N_3$ 분말을 첨가하여 (Ga,Mg)N 나노선을 성공적으로 합성하였다. 합성시에 GaN와 Mg 소스간의 거리 변화를 통해 Mg 도핑농도를 제어하고자 하였다. 이 같은 방법으로 합 된 (Ga,Mg)N 나노선의 Mg 도핑농도에 따른 결정학적 특성을 알아보고, (Ga,Mg)N 나노선을 이용하여 소자를 제작한 후 그 전기적 특성을 살펴보고자 한다. X-ray diffraction (XRD)과 high-resolution transmission electron microscopy (HRTEM), EDX를 이용하여 합성된 나노선의 결정학적 특성과 Mg의 도핑 농도를 확인하였다. Photo lithography와 e-beam lithography법을 이용하여 (Ga,Mg)N 나노선 field-effect transistor (FET)를 제작하고, channel current-drain voltage ($I_{ds}-V_{ds}$) 와 channel current-gate voltage ($I_{ds}-V_g$) 측정을 통해 (Ga,Mg)N 나노선이 도핑 농도에 따라 n형에서 p형으로 전기적 특성이 변화함을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.477-478
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• 2019

We have investigated the experiments in which fabrication and characterization of single-electron transistors were conducted due to easy fabrication and high functionality. In the Fe-MgF2 granular film, in which Fe grains are distributed between insulators instead of the conventional quantum dots, it can be easily fabricated by EB deposition alone, and various output values can be expected by applying two or more gate voltages. The tunneling thickness of the film for single-electron operation was investigated and it was confirmed that the tunneling occurred at 2.1 nm.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.8 no.6
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• pp.939-946
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• 2018

In this work, we present simple schematics for a three-terminal graphene-based nanoelectromechanical switch with the vertical electrode, and we investigated their operational dynamics via classical molecular dynamics simulations. The main structure is both the vertical pin electrode grown in the center of the square hole and the graphene covering on the hole. The potential difference between the bottom gate of the hole and the graphene of the top cover is applied to deflect the graphene. By performing classical molecular dynamic simulations, we investigate the nanoelectromechanical properties of a three-terminal graphene-based nanoelectromechanical switch with vertical pin electrode, which can be switched by the externally applied force. The elastostatic energy of the deflected graphene is also very important factor to analyze the three-terminal graphene-based nanoelectromechanical switch. This simulation work explicitly demonstrated that such devices are applicable to nanoscale sensors and quantum computing, as well as ultra-fast-response switching devices.

• Journal of the Korean Vacuum Society
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• v.21 no.5
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• pp.273-278
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• 2012

Over the last decade, the hafnium-based gate dielectric materials have been studied for many application fields. Because these materials had excellent behaviors for suppressing the quantum-mechanical tunneling through the thinner dielectric layer with higher dielectric constant (high-K) than $SiO_2$ gate oxides. Although high-K materials compensated the deterioration of electrical properties for decreasing the thickness of dielectric layer in MOSFET structure, their nano-mechanical properties of $HfO_2$ thin film features were hardly known. Thus, we examined nano-mechanical properties of the Hafnium oxide ($HfO_2$) thin film in order to optimize the gate dielectric layer. The $HfO_2$ thin films were deposited by rf magnetron sputter using hafnium (99.99%) target according to various oxygen gas flows. After deposition, the $HfO_2$ thin films were annealed after annealing at $400^{\circ}C$, $600^{\circ}C$ and $800^{\circ}C$ for 20 min in nitrogen ambient. From the results, the current density of $HfO_2$ thin film for 8 sccm oxygen gas flow became better performance with increasing annealing temperature. The nano-indenter and Weibull distribution were measured by a quantitative calculation of the thin film stress. The $HfO_2$ thin film after annealing at $400^{\circ}C$ had tensile stress. However, the $HfO_2$ thin film with increasing the annealing temperature up to $800^{\circ}C$ had changed compressive stress. This could be due to the nanocrystal of the $HfO_2$ thin film. In particular, the $HfO_2$ thin film after annealing at $400^{\circ}C$ had lower tensile stress, such as 5.35 GPa for the oxygen gas flow of 4 sccm and 5.54 GPa for the oxygen gas flow of 8 sccm. While the $HfO_2$ thin film after annealing at $800^{\circ}C$ had increased the stress value, such as 9.09 GPa for the oxygen gas flow of 4 sccm and 8.17 GPa for the oxygen gas flow of 8 sccm. From these results, the temperature dependence of stress state of $HfO_2$ thin films were understood.

• Journal of Internet Computing and Services
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• v.23 no.3
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• pp.47-56
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• 2022

The safe driving reward system aims to reduce the loss of life and property by reducing the occurrence of accidents by motivating safe driving and encouraging active participation by providing direct reward to vehicle drivers who have performed safe driving. In the case of the existing digital tachograph, the goal is to limit dangerous driving by recording the driving status of the vehicle whereas the safe driving reward system is a support measure to increase the effect of accident prevention and induces safe driving with financial reward when safe driving is performed. In other words, in an area where accidents due to speeding are high, direct reward is provided to motivate safe driving to prevent traffic accidents when safe driving instructions such as speed compliance, maintaining distance between vehicles, and driving in designated lanes are performed. Since these safe operation data and reward histories must be managed transparently and safely, the reward evidences and histories were constructed using the closed blockchain Hyperledger Fabric. However, while transparency and safety are guaranteed in the blockchain system, low data processing speed is a problem. In this study, the sequential block generation speed was as low as 10 TPS(transaction per second), and as a result of applying the acceleration function a high-performance network of 1,000 TPS or more was implemented.