• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The KIPS Transactions:PartB
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• v.11B no.3
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• pp.289-296
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• 2004

General watermarking techniques tend not to consider intrinsic characteristics of image, so that watermarks are embeded to entire images. In this paper, we present a watermarking algorithm based on wavelet domain, and the watermark is embedded into large coefficients in region of interest(ROI) being based on principle of multi-threshold watermark coding(MTWC) for robust watermark insertion. We try to accomplish both image duality and robustness using human visual system(HVS). The watermarks are embedded in middle frequency bands because the distortion degree of watermarked images appears to be less than lower frequency bands, and the embedded watermarks in the middle bands showed high extraction ratios after some distortion. The watermarks are consisted of pseudo random sequences and detected using Cox's similarity mesurement.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3290-3299
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• 2000

Digital watermarking has similar concepts with channel coding thechnique for transferring data with minimizing error in noise environment, since it should be robust to various kinds of data manipulation for protecting copyrights of multimedia data. This paper proposes a digital watermarking technique which is robust to various kinds of data manipulation. Intellectual property rights information is encoded using a convolutional code, and block-interleaving technique is applied to prevent successive loss of encoded data. Encoded intelloctual property rithts informationis embedded using spread spectrum technique which is robust to cata manipulation. In order to reconstruct intellectual property rights information, watermark signalis detected by covariance between watermarked image and pseudo rando noise sequence which is used to einbed watermark. Embedded intellectual property rights information is obtaned by de-interleaving and cecoding previously detected wtermark signal. Experimental results show that block interleaving watermarking technique can detect embedded intellectial property right informationmore correctly against to attacks like Gaussian noise additon, filtering, and JPEG compression than general spread spectrum technique in the same PSNR.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.5
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• pp.1058-1068
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• 2017

In V2X communication, a random based resource selection scheme is needed with considerations of cases that support devices without sidelink reception capabilities and require reduction of UE's power consumption. In this paper, as improvement of D2D's resource section scheme that one TRP is repeated to data subframe pool within a PSCCH period, it is proposed that different TRPs is applied for enhanced random resource selection based on pseudo-random sequence having UE-specific seed value. By results of proposed scheme's performance by numerical analysis, it is confirmed that collision probability among resources allocated to each UE for data TB is reduced, and a number of UEs which can avoid resource collision as much as possible and have simultaneous resource allocation is increased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3688-3693
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• 2009

In this paper the design methode of a separated composition state machine based on the compositive map with connecting two chaotic maps together - sawtooth map $S_2(x)$ and tent map $T_2(x)$ and the result of that is proposed. this paper gives a graph of the chaotic states generated by the composition state machine using the compositive logic of two different chaotic maps - sawtooth map and tent map and also shows that the period of pseudo-random states has the length according to the precision of the discreet truth table.

• Journal of Positioning, Navigation, and Timing
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• v.2 no.1
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• pp.1-8
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• 2013

A signal system for improving the code acquisition complexity of Global Navigation Satellite System (GNSS) receiver is proposed and the receiving correlator scheme is presented accordingly. The proposed signal system is a hierarchical code type with a duplexing configuration which consists of the Zadoff-Chu (ZC) code having a good auto-correlation characteristic and the Pseudo Random Noise (PRN) code for distinguishing satellites. The receiving correlator has the scheme that consists of the primary correlator for the ZC code and the secondary correlator which uses the PRN code for the primary correlation results. The simulation results of code acquisition using the receiving correlator of the proposed signal system show that the proposed signal scheme improves the complexity of GNSS receiver and has the code acquisition performance comparable to the existing GNSS signal system using Coarse/Acquisition (C/A) code.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.1
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• pp.179-184
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• 2020

Cellular automata (CA), which is known as a pseudo random number generator due to its excellent randomness, has various applications. Cho et al. designed a CA-based shrinking generator to generate a long period of nonlinear sequence. In addition, chaotic cat maps have been studied by many researchers as the complex nonlinear dynamics systems with sensitivity in initial conditions and unpredictable characteristics. In this paper, we propose a new image encryption method using nonlinear sequence generated by CA-based shrinking generator with maximum period and 3D chaotic cat map for high security.

• Journal of Digital Contents Society
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• v.5 no.3
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• pp.219-224
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• 2004

In This paper, we have analyzed the power spectrum of DS-TH Ulhawideband (Direct Sequence-Time Hopping UWB) system which used pseudo-noise (PN) code. The DS-TH UWB system proposed in this paper multiplies the information signal with PN code to construct pulse train with random pattern and then the chips in pulse train are bundled into several groups to map to the particular value. The (+)/(-) pulse is tented in the time slot of frame by comparing a particular value with timing information that was stored in the lookup table. Thus, the energy spark (Comb Line) which is generated certainly in convantional system can be suppressed efficiently by PN code. And we knew that the proposed DS-TH UWB System even could have very smoothing power spectrum ctaracteristic without applying high speed Time-Hopping code.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.6
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• pp.1105-1112
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• 2020

One-dimensional 3-neighborhood Cellular Automata (CA)-based pseudo-random number generators are widely applied in generating test patterns to evaluate system performance and generating key sequence generators in cryptographic systems. In this paper, in order to design a CA-based key sequence generator that can generate more complex and confusing sequences, we study a one-dimensional symmetric 5-neighborhood CA that expands to five neighbors affecting the state transition of each cell. In particular, we propose an n-cell one-dimensional symmetric 5-neighborhood CA synthesis algorithm using the algebraic method that uses the Krylov matrix and the one-dimensional 90/150 CA synthesis algorithm proposed by Cho et al. [6].

• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.