• 제목/요약/키워드: programmable network

검색결과 136건 처리시간 0.021초

CIM을 위한 Mini-MAP 네트워크 접속장치의 구현에 관한 연구 (A Study on the Implemention of a Mini-MAP Network Interface Module for CIM)

  • 김현기;이전우;하정현;정하재;채영도
    • 전자공학회논문지B
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    • 제30B권10호
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    • pp.59-68
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    • 1993
  • This paper describes implemation of 'General-purpose ETRI MAP interface module' (GEM) for Mini-MAP network. GEM operates as a Mini-MAP node in our FA system. To communicate between GEM and programmable devices(PD) such as PLC and CNC, serial communication is used. Application programs of a MiNi-MAP host system control and monitor programmable devices via GEM. GEM is implemented and tested on the basis of the MAP 3.0. TBC in the Nini-MAP board performs the function of the MAC sublayer. The LLC sublayer is implemented according to the specification of Class 3 that includes Type 1 and 3. And the MMS services are designed within the scope of implementation class MAP3. All the softwares are implemented under the real-time multitask OS for real-time application of the Mini-MAP and they are loaded into PROMs at the network board of GEM. We tested the LLC functions to make use of a protocol analyzer for the token-passing protocol. Also the MMS conformance test was carried out by exchanging primitives between GEM and a MMS product that had already passed the conformance test. Therefore GEM is proposed as a network tool of Computer Integrated Manufacturing (CIM) to integrate PDs which don't support MAP functions.

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Low area field-programmable gate array implementation of PRESENT image encryption with key rotation and substitution

  • Parikibandla, Srikanth;Alluri, Sreenivas
    • ETRI Journal
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    • 제43권6호
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    • pp.1113-1129
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    • 2021
  • Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

Design and Implementation of Low-Cost Articulate Manipulator for Academic Applications

  • Muhammad Asim Ali;Farhan Ali Shah
    • International Journal of Computer Science & Network Security
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    • 제24권1호
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    • pp.17-22
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    • 2024
  • The objective of this work is to design a low cost yet fully functional 4-DOF articulate manipulator for educational applications. The design is based on general purpose, programmable smart servo motors namely the Dynamixel Ax-12. The mechanism for motion was developed by formulating the equations of kinematics and subsequent solutions for joint space variables. The trajectory of end-effector in joint variable space was determined by interpolation of a 3rd order polynomial. The solutions were verified through computer simulations and ultimately implemented on the hardware. Owing to the feedback from the built-in sensors, it is possible to correct the positioning error due to loading effects. The proposed solution offers an efficient and cost-effective platform to study the trajectory planning as well as dynamics of the manipulator.

휴대 단말기상의 프로그래머블 가상 머신을 이용한 심전도(ECG) 신호 모니터링 시스템 (Remote ECG Monitoring System Using Mobile Handset with Programmable Virtual Machine)

  • 정궁;민홍기;이응혁;홍승홍
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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    • pp.2899-2902
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    • 2003
  • Mobile communication is one of the fastest growing industries in the world and especially in Korea, where we have well over 30 million voice subscribers. Mobile communication now offers variety of data communication services such as wireless internet, multimedia messages, and color graphic displays. Handsets also have grown to accommodate such services, thus with functionalities such as programmable virtual machines that users can download and execute their own programs. In this paper, we have demonstrated a PCS handset monitoring system which can monitor biometry signals - in this case ECG over wireless internet and wireless data network (IS95C) based on programmable virtual machine architecture. The remote client handset receives data signals from a centralized server and processes and displays them in human friendly form in real time. Since every single handset on sales in Korea has programmable virtual machine and more than 10 million handsets are in distribution already, proper applications may have substantial impact on the related fields.

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하드웨어 기반 Anti-DDoS 대응 장비 고속 패킷 필터링을 위한 Hi-DPI 알고리즘 연구 (Development Hi-DPI Algorithm for High Speed Packet Filtering of Anti-DDoS based on HW)

  • 김점구
    • 융합보안논문지
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    • 제17권2호
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    • pp.41-51
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    • 2017
  • 인터넷 활용 범위의 폭발적인 증가는 점차적으로 네트워크 속도와 용량을 초고속화 하고 대용량화로 빠르게 진화해 가고 있다. 이에 따라 스위치 라우터 등 네트워크 장비들은 하드웨어에 기반 한 빠른 기술 진화로 대처를 하고 있으나 초연결사회에 가장 기본적이고 필수적인 네트워크 보안시스템의 기술 진화는 수만 가지의 보안 이슈와 시그니처(signature)에 대해서 수시 변경과 갱신을 필요로 하기 때문에 소프트웨어에 기반 한 기술적인 한계를 극복하기가 쉽지 않다. 본 논문은 이와 같은 DDoS 대응 장비를 설치 운영할 때의 패킷 필터링 속도 저하 문제점을 개선하고자 FPGA(Field Programmable Gate Array)의 하드웨어적인 특성과 병렬처리 특성을 최대한 반영한 DPI 알고리즘인 Hi-DPI를 제안하고 실용성을 검증하고자 한다.

SRv6 기반 네트워크 프로그래밍 기술 동향 (Technology Trends in Network Programming Based on SRv6)

  • 유현경 ;장석원;고남석
    • 전자통신동향분석
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    • 제38권2호
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    • pp.36-45
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    • 2023
  • Segment routing (SR) is a source-based routing architecture in which a node steers packets adhering to service and topological requirements. Using programmable segments, SR enables end-to-end service connectivity to satisfy the network constraints of various services. SR can be implemented with both MPLS and IPv6 dataplanes. This survey presents the overview of SR for IPv6 dataplane (SRv6), network programming technologies based on SRv6, and the SR deployment status.

표준 API에 의한 IP 라우터 설계 (Design of an IP Router with Application Programming Interfaces)

  • 주성순;정영식
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.799-802
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    • 1999
  • In this paper, programmable abstractions of the underlying resources of the IP router are proposed for designing a software architecture of the next generation router, which can provide the variety of QoS services and reliable and complicate network services.

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Expert Network의 모듈형 계층구조를 이용한 범용 연산회로 설계 (General Purpose Operation Unit Using Modular Hierarchical Structure of Expert Network)

  • 양정모;홍광진;조현찬;서재용;전홍태
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 2003년도 추계 학술대회 학술발표 논문집
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    • pp.122-125
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    • 2003
  • By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

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Sensor Utility Network를 위한 저전력 Burst 클록-데이터 복원 회로를 포함한 클록 시스템 (A Clock System including Low-power Burst Clock-data Recovery Circuit for Sensor Utility Network)

  • 송창민;서재훈;장영찬
    • 전기전자학회논문지
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    • 제23권3호
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    • pp.858-864
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    • 2019
  • 본 논문에서는 센서 유틸리티 네트워크에서 센서 노드들 사이의 주파수 차이로 인한 데이터 손실을 제거하기 위한 클록 시스템이 제안된다. 각 센서 노드를 위한 제안된 클록 시스템은 버스트 클록-데이터 복원 회로, 32-위상 클록을 출력하는 디지털 위상 고정 루프, 그리고 프로그래밍 가능한 개방형 루프 분수 분할기를 사용하는 디지털 주파수 합성기로 구성된다. 첫번째 센서 노드에는 버스트 클록-데이터 복원 회로 대신 능동 인덕터를 사용하는 CMOS 발진기가 사용된다. 제안된 클록 시스템은 1.2 V 공급 전압을 이용하는 65nm CMOS 공정에서 설계된다. 센서 노드들 사이의 주파수 오류가 1%일 때, 제안하는 버스트 클록-데이터 복원 회로는 기준 클록으로 5Mbps 데이터 속도에 대해 64배 체배된 주파수를 가짐으로 4.95 ns의 시간지터를 가진다. 설계된 디지털 주파수 합성기의 주파수 변경은 100 kHz에서 320 MHz의 주파수 범위에서 출력 클록의 한 주기 내에 수행된다.

보울 피이더에서 신경 회로망을 이용한 부품 자세 인식에 관한 연구 (A neural network method for recognition of part orientation in a bowl feeder)

  • 임태균;김종형;조형석;김성권
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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    • pp.275-280
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    • 1990
  • A neural network method is applied for recognizing the orientation o f individual parts being fed from a bowl feeder. The system is designed in such a way that a part can be discriminated and sorting according to every possible stable orientation without implementing any a mechanical tooling. The operation of the bowl feeder is based on a 2D image obtained from an array of fiber optic sensor located on the feeder track. The acquired binary image of a moving and vibrating part is used as input to a neural network which, in turn, determines t he orientation of the part. The main task of the neural network, here is to synthesize the appropriate internal discriminant functions for the part orientation using the part features. A series of the experiments reveals several promising points on performance. Since the operation of the feeder is highly programmable, it is well suited for feeding and sorting small parts prior to small batch assembly work.

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