• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.2
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• pp.365-375
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• 2019

A PLC (Programmable Logic Controller) is a highly-reliable industrial digital computer which supports real-time embedded control applications for safety-critical control systems. Real-time operating systems such as uC/OS have been used for PLCs and must meet real-time constraints. As PLCs have been widely used for industrial control systems and connected to the Internet, they have been becoming a main target of cyberattacks. In this paper, we propose an execution code sanitizer to enhance the security of PLC systems. The proposed sanitizer analyzes PLC programs developed by an IDE before downloading the program to a target PLC, and mitigates security vulnerabilities of the program. Our sanitizer can detect vulnerable function calls and illegal memory accesses in development of PLC programs using a database of vulnerable functions as well as the other database of code patterns related to pointer misuses. Based on these DBs, it detects and removes abnormal use patterns of pointer variables and existence of vulnerable functions shown in the call graph of the target executable code. We have implemented the proposed technique and verified its effectiveness through experiments.

• Journal of KIISE
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• v.43 no.5
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• pp.569-578
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• 2016

The PLC (Programmable Logic Controller) has been widely used for the development of digital control system of nuclear power plant. The PLC has high maintenance costs and increasing complexity, hence, FPGA (Field Programmable Gate Array) based digital control system has been considered as an alternative. However, the development of FPGA based digital control system is a challenge for PLC engineers because they are required to learn about new language to develop FPGA and knowledge and know-how acquired in the development of PLC is not transferable. In this study, we proposed and implemented an automatic translation tool for translation of FBD (Function Block Diagram), a programming language of PLC software, into VHDL (VHSIC Hardware Description Language). Automatically translating the FBD to VHDL using this tool allows PLC engineers to develop FPGA without any knowledge of the hardware description language.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.9
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• pp.39-46
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• 2007

This paper presents a programmable single-phase ac power source that provides a sinusoidal output voltage with an adjustable output amplitude and frequency over a wide range as well as an arbitrary waveform. The ac power source under consideration have a linear power amplifier. The desired output values can be programmed with a personal computer. The power source operates at 220[V]/60[Hz] mains and the output voltage is isolated from the input circuit. The system consists mainly of a power converter to generate and amplify the waveform signal, a controller to control the desired output signal and measure the output parameters, and a control program to set the desired output and display the values. The prototype ac power source was constructed and tested with the results demonstrating a good performance.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.438-451
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• 1994

A low complexity, fault detecting computer architecture for utilisation in programmable logic controllers is designed. The cyclic operating mode of PLCs and a specification level, graphical programming paradigm based on the interconnection of application oriented standard software function modules are architecturally supported. Thus, by design, there is no semantic gap between the programming and machine execution levels enabling the safety licensing of application software by an extremely simple, but rigorous method, viz, diverse back translation.

• Proceedings of the KSR Conference
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• 2003.05a
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• pp.427-432
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• 2003

The control method of programmable dynamometer for overall test of machine is to load the reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of moter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for meter torque of programmable dynamometer. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction meter. Therefore, the torque controller is not affected by a load torque disturbance.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1108-1110
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• 2003

The control method of programmable dynamometer for overall test of machine is to load the reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of meter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for meter torque of programmable dynamometer. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction moter. Therefore, the torque controller is not affected by a load torque disturbance.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.169-170
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• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.6
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• pp.370-479
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• 1988

This paper presents a microprogrammable sequential controller which realizes the sequential logic system with parallel sequences described by a GRAFCET. The proposed controller improves speed, flexibility, programming ease and the efficiency of controlled system by paralle sequencing capability. It is especially designed for complex high speed sequential contollers requiring large I/O capabilities, such as industrial process controller or power electronic conversion controller.