• Korean Journal of Computational Design and Engineering
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• v.14 no.3
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• pp.176-185
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• 2009

Modern manufacturing systems consist of highly automated manufacturing devices, and they are controlled by complicated PLC programs. To make sure the achievement of the control objectives of a manufacturing system, it is very important to monitor the dynamic system behaviors of the manufacturing system. In this paper, we propose a monitoring methodology of a PLC program based on the Software In the Loop Simulation(SILS), which makes use of the time gap information between PLC signals. The errors relevant with PLC signals can be found using the proposed methodology, comparing a normal PLC signal trajectory with a target PLC signal trajectory. The proposed methodology has been implemented and tested with simple examples.

• Korean Journal of Computational Design and Engineering
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• v.14 no.1
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• pp.50-59
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• 2009

There are two main problems in the current PLC ladder programming practices: First, currently there are no widely adopted systematic design methods to deal with PLC based control systems in the shop floor. So, the control logic design phase is usually omitted in current PLC programming development life cycle. Second, PLC ladder logic provides only microscopic view of system processes. As a result, it is difficult for FA engineers to have overall perspectives about the interaction of system components intuitively during the verification step of logic errors. To solve these problems, this paper proposed object-oriented design and automatic generation method of PLC ladder logic. Based on the proposed method, the computer software to assist the automatic ladder logic generation is also developed.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2001.05a
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• pp.26-31
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• 2001

Petri nets(PN) have been introduced as a poweful analyzing and design tool for the discrete systems such as sequential control systems. However, one of the important problems in its applications is that the model can not be analyzed easily when we deal with large scale systems because of increase of the number of components of the systems. To overcome this problem, some methods for dividing or reducing of PN have been suggested. In this paper, an approach for hierarchical expression of PN based on Sequential Function Chart(SFC) and Bottom Up oriented Mehodology(BUM) is proposed. Especially, some definition and rules are defined in order to divide and compose sub PN. A measuring tank system will be described as a typical kind of discrete systems and modeled by some sub PN based on the SFC and BUM by the proposed method in this paper.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.2
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• pp.54-61
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• 1998

Ladder Diagram(LD) is the most extensively used among Programmable Logic Controller(PLC) standard languages for the design of process control system with PLC. But LD has the disadvantages for data processing and maintenance. On the other hand, there is full support for describing sequences so that complete sequential behavior can be easily broken down using a concise graphical language called Sequential Function Chart(SFC). Inspite of those characteristics, SFC is not suitable for describing interlock logic. In this paper, we propose the method for implementing interlock logic by using conventional SFC compiler and verify the effectiveness by applying proposed scheme to the In-Line Spin Coater.Coater.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2390-2392
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• 1998

In this paper, we discuss the development of monitoring system with data process equipment which transfers data from Remote Terminal Unit(RTU) to monitoring computer. The RTUs sense temperature, pressure and PLC(Programmable Logic Controller) nodes conditions of scrubber in semiconductor manufacture processing. The data Process equipment is connected every RTU and a monitoring computer through serial communication. This equipment receives informations from RTU, process data, and transfers them to monitoring computer. To avoid congestion in data communication, task scheduling algorithm used RT O/S(Real-Time Operating System) is embedded in ROM which is a part of data Process equipment.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.475-477
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• 1998

In this paper, the implementation of a virtual Plant simulator for the PLC programming is presented. A virtual plant simulator that replaces function of transducers (e.g. pumps and valves) consists of a personal computer and a PLC(Programmable logic controller). Input/output conponents are edited on the monitor and are operated as the field transducers. The timing process for input/output components is analyzed. The data flow between a PLC system and a virtual plant simulator is carried out.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.880-882
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• 1995

The systematic function of the PLC (Programmable - Logic Controller) has been enhanced immensely due to the various special modules that consist of the conventional I/O control contants plus special function, which enables the flexible application to highly advanced systems. Position control module is one of the various PLC special module. In this paper, we proposed new synchronized operating method and implemented 8 - axis servo control system. The validity of proposed method is verified througth experimental results and it will be possible to expand 32 - axis servo control system by RS - 485 communication spec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.124-132
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• 1987

In this paper, a new Open and Closed Loop Alternation(OCLA) frequency synthesizer is developed to eliminate a frequency error occurring in the transition state of a frequency hopping. This frequency synthesizer consists of a phase comparator(PC), two low pass filters(LPF), two voltage controlled oscillators(VCO), switching elements, a programmable divider and frequency hopping controller, and the stabilized output frequency can be obtained by switching performance. In addigion, it can be found that the characteristic of its circuit construction makes it easy to attach an external circuitry to the open loop.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1390-1393
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• 1993

An 8b Fuzzy Coprocessor (FC) is presented that has eight programmable fuzzy algorithms and up to 256 inputs, 64 outputs and 16,384 rules. The 6.4mm2 chip fabricated in 1.0$\mu\textrm{m}$ CMOS technology can be used as a stand-alone device or as a macrocell for microcontrollers. Operating at 20MHz crystal frequency, it has a peak performance of 7.9M rules/s. Perspectives of future FC generations are also outlined, including a 12-16b resolution, additional fuzzy set operations, and optimized inference and defuzzification strategies.

• Journal of Communications and Networks
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• v.18 no.1
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• pp.40-49
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• 2016

In this paper, we present a symbol-level iterative source-channel decoding (ISCD) algorithm for reliable transmission of variable-length codes (VLCs). Firstly, an improved source a posteriori probability (APP) decoding approach is proposed for packetized variable-length encoded Markov sources. Also proposed is a recursive implementation based on a three-dimensional joint trellis for symbol decoding of binary convolutional codes. APP channel decoding on this joint trellis is realized by modification of the Bahl-Cocke-Jelinek-Raviv algorithm and adaptation to the non-stationary VLC trellis. Simulation results indicate that the proposed ISCD scheme allows to exchange between its constituent decoders the symbol-level extrinsic information and achieves high robustness against channel noises.