• Title/Summary/Keyword: programmable controller

Search Result 441, Processing Time 0.033 seconds

Fault-tree Analysis Modeling for Bus Structure of High Reliable Redundant Controller (고신뢰성 다중화 제어기기의 버스구조에 대한 결함수목분석(Fault-tree Analysis) 모델링)

  • Noh, Jinpyo;Kim, Joonkyo;Son, Kwang-Seop;Kim, Dong-Hoon;Park, Jaehyun
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2012.11a
    • /
    • pp.87-90
    • /
    • 2012
  • 원자력발전소에 사용되는 모든 시스템은 IEEE에서 최고 수준의 안전도인 CLASS 1E로 분류된다. 그중에서 안전계통은 원자력발전소 안전에 관련한 모든 분야를 관리하는 계통이다. 산업이 발전함에 따라 안전계통 또한 그 규모와 복잡성이 높아지고 있고, 이에 적용되는 요구사항 또한 엄격해지고 있다. 따라서 발전소에 적용되는 안전 동작에 대한 기준을 결정하기 위해서 철저한 오류 예측분석이 수행 되어야 한다. 그 중에서도 NUREG-0492로 규정되어 있는 결함수목분석(Fault Tree Analysis)은 연역적 오류 예측 분석방법으로 원자력 발전소, 우주 산업 등에 관련된 분야는 본 방법을 통하여 오류 예측 분석이 이루어 져야한다. 본 논문에서 원전안전계통을 관리하는 구현 모델인 원전안전등급제어기기(Safety Programmable Logic Controller)에 대하여 결함수목분석을 통한 오류 예측 분석을 하였다. 또한, 위의 구조에 대하여 MSC(Message Sequence Chart)를 통한 모델링을 수행하여, 결함수목분석을 적용하는 과정에서 신뢰도 향상을 더하였다.

DEVELOPMENT OF THE READOUT CONTROLLER FOR INFRARED ARRAY (적외선검출기 READOUT CONTROLLER 개발)

  • Cho, Seoung-Hyun;Jin, Ho;Nam, Uk-Won;Cha, Sang-Mok;Lee, Sung-Ho;Yuk, In-Soo;Park, Young-Sik;Pak, Soo-Jong;Han, Won-Yong;Kim, Sung-Soo
    • Publications of The Korean Astronomical Society
    • /
    • v.21 no.2
    • /
    • pp.67-74
    • /
    • 2006
  • We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

An Electronic Ballast Using A Multiplex Modulation Method for The Metal Halide Lamp (다중 변조식 메탈 할라이드 램프용 고주파 전자식 안정기)

  • Oh, Duk-Jin;Kim, Hee-Jun;Oh, Won-Seok;Cho, Kyu-Min
    • Proceedings of the KIEE Conference
    • /
    • 2002.07b
    • /
    • pp.1129-1133
    • /
    • 2002
  • This paper presents an electronic ballast using a novel multiplex modulation method for the metal halide lamp. The proposed modulation method, which has a modulating signal of swept multiplex frequency, can eliminate the acoustic resonance more effectively than the conventional modulation method, which has a modulating signal of constant frequency. For the purpose of future application specific integrated circuits (ASIC), the controller of the proposed ballast has been designed only with erasable programmable logic devices (EPLDs), but without a microprocessor. In this paper, detailed proposed modulation schemes are described and experimental results on the proto-type 150W metal halide lamp ballast with the proposed modulation method are discussed.

  • PDF

Study on the Composition of Subsystem Designed by Hierarchical Control Structure of SFC (SFC의 계층제어구조로 설계된 서브시스템 결합에 관한 연구)

  • You, Jeong-Bong
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.20 no.4
    • /
    • pp.49-55
    • /
    • 2006
  • In industrial control system used by Programmable Logic Controller(PLC), ladder Diagram(LD) is the must widely utilized and plays an important role in industrial control system. But recently, the study about Sequential Function Chart(SFC) is performed actively. When we program by SFC, generally, we design one routine from start to end. This method is difficult to design, and we often make mistakes. In this paper, we propose the method that we compose each sub-system after we design each sub-system and confirm his feasibility through an actual examples.

Implementation of Position Control of PMSM with FPGA

  • Reaugepattanawiwat, Chalermpol;Eawsakul, Nitipat;Watjanatepin, Napat;Pinprathomrat, Prasert;Desyoo, Phayung
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 2004.08a
    • /
    • pp.1254-1258
    • /
    • 2004
  • This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

  • PDF

Development of the proto type vacuum control system for RAON Accelerator

  • Son, Hyeong-Ju;Lee, Sang-Il;Park, Mi-Jeong
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2016.02a
    • /
    • pp.121.1-121.1
    • /
    • 2016
  • RAON은 우라늄과 같은 무거운 이온을 가속시키는 한국형 중이온 가속기로서 현재 양산에 필요한 실험 시설이 구축되고 있다. 이온원을 생성하고 생성된 중이온 빔을 손실 없이 가속시키기 위해서는 빔의 경로인 입사기장치, 가속장치, 실험장치에서 요구하는 최적의 진공 설계가 이루어져야 하며, 이를 제어하기 위해 진공 기기들과의 데이터 통신 및 기기를 보호하기 위한 인터록 로직을 구성하여야 한다. RAON의 진공부 인터록 로직 및 제어 시퀀스는 Programmable Logic Controller (PLC)으로 구성되며, Experimental Physics and Industrial Control System (EPICS) 환경에 통합되어 중앙 제어 시스템에서 관리됨과 동시에 Control System Studio (CSS)를 통해 모니터링 될 것이다. 이를 위해서는 CSS 및 PLC 와 데이터를 송수신할 수 있는 EPICS IOC를 구성하여야 한다. 본 문서에서는 진공 기기들의 정보를 로컬 PLC에서 수집하고, 진공 상태 및 진공 기기들의 작동을 위한 User Interface (UI) 및 EPICS IOC를 구성하는 방법에 대해 논의할 것이다. 진공부 제어 사전 테스트를 위해 프로토 타입 진공 제어 시스템을 구성하였으며, 이를 바탕으로 추후 최적화 된 RAON의 진공 제어 시스템을 구축할 수 있을 것으로 기대한다.

  • PDF

Technology Trend of Developing High-Speed and High-Performance Parcel Sorter (고속·고효율 소포구분기 개발기술 동향)

  • Choi, C.Y.;Choi, Y.H.;Jung, H.
    • Electronics and Telecommunications Trends
    • /
    • v.28 no.4
    • /
    • pp.53-63
    • /
    • 2013
  • 전세계적으로 우편 물량의 감소, 민간 사업자와의 경쟁심화 등의 환경 변화 속에서 안정적 우편수익을 창출하고 소포우편물의 소통품질을 향상하기 위해 주요국 우편사업자들은 단시간에 우편물 처리를 자동으로 구분하여 자동 처리율을 극대화하기 위한 방안을 모색하고 있다. 국내 우정사업본부도 신규 도입 및 교체 시기가 도래함에 따라 중장기적 관점의 신규 소포구분기의 도입계획 수립하였다. 그 일환으로 소포구분기의 표준 규격을 마련하고 소포구분기의 국산화에 박차를 가하여 향후 도입 비용 및 유지보수 비용을 절감하기 위해 노력하고 있다. 세부적으로 국내 PLC(Programmable Logic Controller) 및 제어 장비를 통해 제어 기술을 확보하고 표준화된 운영이 가능토록 현존 소프트웨어 시스템의 고도화를 통해 소통품질 및 업무성과 개선 기술을 실제 현장 운영을 통해 개발 검증 중이다.

  • PDF

Interfacing Module Design for Real Time Processing in Distributed Programmable Devices (분산된 단위 제어기기의 실시간 처리를 위한 접속 모듈의 설계)

  • 박남수;김정호;이상범
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.30B no.9
    • /
    • pp.9-17
    • /
    • 1993
  • There are multiple controllers (PLC. LOOP Controller ) which are operating in product line and fabrication line. In those lines, it is necessary to connect various multilple controllers with integrity and coordination. The ways to connect those devices are specified by ISO network standard. In this paper, real time network is designed and implemented for factory automation at lowest possible cost that meets the small and middle size MINI-MAP specifications. Network performance is evaluated by simulation method on data link layer implemented interfacing modules has efficiency in throughput by reducing processing time. The system designed in this paper can be also applied to the field of distributed systems for real time processing.

  • PDF

A basic study on the application of the softwired sequence control to the interface of NC mahine tool (NC공작기계 Interface의 Softwired Sepuence Control화를 위한 기초연구)

  • ;;Lee, Hyung Sik;Hyun, Chang Hyun
    • Transactions of the Korean Society of Mechanical Engineers
    • /
    • v.5 no.3
    • /
    • pp.207-216
    • /
    • 1981
  • Recently in some nations, the interface of NC machine tool is by applying the softwired sequence control method which employs the PLE(Programmable Logic Controller) instead of the hardwired sequence control method. Due to this replacament, the funcion of the interface of NC machine tool has been improved in many respects. In order to accomplish such as improvement of the function of the interface and to develop the PLC, this paper deals with how to apply the sofrwired sequence control method that employs microcumputer to the interface of ATC(Automatic Tool Changer) which is a part of NC lathe.

A Formal Safety Analysis for PLC Software-Based Safety Critical System using Z

  • Koh, Jung-Soo;Seong, Poong-Hyun;Son, Han-Seong
    • Proceedings of the Korean Nuclear Society Conference
    • /
    • 1997.05a
    • /
    • pp.153-158
    • /
    • 1997
  • This paper describes a formal safety analysis technique which is demonstrated by performing empirical formal safety analysis with the case study of beamline hutch door Interlock system that is developed by using PLC(Programmable Logic Controller) systems at the Pohang Accelerator Laboratory. In order to perform formal safety analysis, we have built the Z formal specifications representation from user requirement written in ambiguous natural language and target PLC ladder logic, respectively. We have also studied the effective method to express typical PLC timer component by using specific Z formal notation which is supported by temporal history. We present a formal proof technique specifying and verifying that the hazardous states are not introduced into ladder logic in the PLC-based safety critical system.

  • PDF