• Journal of Power Electronics
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• v.14 no.4
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• pp.733-741
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• 2014

The integration of photovoltaic (PV) energy sources into DC grid has gained considerable attention because of its enhanced conversion efficiency with reduced number of power conversion stages. During the integration process, a local control unit is normally included with every power conversion stage of the PV source to accomplish the process of maximum power point tracking. A centralized monitoring and supervisory control unit is required for monitoring, power management, and protection of the entire system. Therefore, we propose a field-programmable gate array (FPGA) based centralized control unit that integrates all local controllers with the centralized monitoring unit. The main focus of this study is on the process of integrating many local control units into a single central unit. In this paper, we present design and optimization procedures for the hardware implementation of FPGA architecture. Furthermore, we propose a transient analysis and control design methodology with consideration of the nonlinear characteristics of the PV source. Hardware experiment results verify the efficiency of the central control unit and controller design.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1151-1172
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• 2014

This paper presents a user programmable computational/control platform developed to conduct real-time hybrid simulation (RTHS). The architecture of this platform is based on the integration of a real-time controller and a field programmable gate array (FPGA).This not only enables the user to apply user-defined control laws to control the experimental substructures, but also provides ample computational resources to run the integration algorithm and analytical substructure state determination in real-time. In this platform the need for SCRAMNet as the communication device between real-time and servo-control workstations has been eliminated which was a critical component in several former RTHS platforms. The accuracy of the servo-hydraulic actuator displacement control, where the control tasks get executed on the FPGA was verified using single-degree-of-freedom (SDOF) and 2 degrees-of-freedom (2DOF) experimental substructures. Finally, the functionality of the proposed system as a robust and reliable RTHS platform for performance evaluation of structural systems was validated by conducting real-time hybrid simulation of a three story nonlinear structure with SDOF and 2DOF experimental substructures. Also, tracking indicators were employed to assess the accuracy of the results.

• IE interfaces
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• v.21 no.3
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• pp.294-301
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• 2008

Agile and flexible manufacturing systems make it mandatory that a control program should have features such as agility, flexibility, and reusability in order to run manufacturing unit smoothly. PLCs are the most frequently used control program in manufacturing systems. PLC programs are mostly programmed by subcontraction, which makes correction of code very difficult. As a result, it may cause delay during down time and ramp up time which leads to big loss of revenue and goodwill. To prevent delay during the times, this paper proposes systematic process analysis and application method for programmable logic controller like LLD (Ladder Logic Diagram). The proposed method uses modified human-error investing techniques for documentation and transforming technique to program LLD from the documentation. Furthermore, this paper demonstrates an example of piston mechanism to explain the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.9-23
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• 2017

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

• Proceedings of the KIEE Conference
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• summer
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• pp.1291-1293
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• 2004

The control method of programmable dynamometer for overall test of machine is to load the reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of meter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for moter torque of programmable dynamometer. Therefore, this kind of system could not perform dynamic and nonlinear load. In this paper, the control method using the load torque observer without a measure for torque transducer is proposed. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction meter. Therefore, the torque controller is not affected by a load torque disturbance.

• Nuclear Engineering and Technology
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• v.45 no.4
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.43-49
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• 2021

A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.