• Journal of Power Electronics
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• v.11 no.4
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• pp.542-550
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• 2011

This paper describes the design and hardware implementation of a Single Input Fuzzy Logic Controller (SIFLC) to regulate the output voltage of a boost power converter. The proposed controller is derived from the signed distance method, which reduces a multi-input conventional Fuzzy Logic Controller (CFLC) to a single input FLC. This allows the rule table to be approximated to a one-dimensional piecewise linear control surface. A MATLAB simulation demonstrated that the performance of a boost converter is identical when subjected to the SIFLC or a CFLC. However, the SIFLC requires nearly an order of magnitude less time to execute its algorithm. Therefore the former can replace the latter with no significant degradation in performance. To validate the feasibility of the SIFLC, a 50W boost converter prototype is built. The SIFLC algorithm is implemented using an Altera FPGA. It was found that the SIFLC with asymmetrical membership functions exhibits an excellent response to load and input reference changes.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2109-2118
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• 2016

Based on the space vector pulse width modulation (SVPWM) theory, this paper realizes an easier SVPWM strategy, which is equivalently implemented by CBSPWM with zero-sequence voltage injection. The traditional SVPWM strategy has no effect on controlling the neutral-point voltage balance. In order to solve the neutral-point voltage unbalance problem for neutral-point-clamped (NPC) three-level inverters, this paper proposes a neutral-point voltage balance controller. The proposed controller realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the three-phase modulation waves of an equivalent SVPWM strategy. Compared with the traditional SVPWM strategy, the proposed neutral-point voltage balance controller has a strong ability to balance the neutral-point voltage, has good steady-state performance, improves the output waveforms quality and is easy for digital implementation. An experiment has been carried out on a NPC three-level inverter prototype based on a digital signal processor-complex programmable logic device (DSP-CPLD). The obtained experimental results verify the effectiveness of the proposed neutral-point voltage balance controller.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.6
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• pp.23-30
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• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.

• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1271-1282
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• 2005

Recently, PC-based control is incredibly developed in the industrial control field, but it is difficult for PLC programming in PC. Therefore, I need to develop the softeware PLC, which support the international PLC programming standard(IECl131-3) and can be applied to diverse control system by using C language. In this paper, I have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user which is used over $90\%$ among the 5 PLC languages, is converted to IL, which is one of intermediate codes, and IL is converted to the standard C rode which can be used in a commercial editor such as Visual C++. In ISPLC, the detection of logical error in high level programming(C) is more eaier than PLC programming itself The study of code conversion of LD->IL->C is firstly tried in the world as well as KOREA. I developed an execution engine with a good practical application. To show the effectiveness of the developed system, 1 applied it to a practical case, a real time traffic control(RT-TC) system. ISPLC is minimized the error debugging and programming time owing to be supported by windows application program.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.2
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• pp.89-96
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• 2016

This paper describes the design of a force measurement and communication system for the force measuring system in industrial robots. The force measurement and communication system is composed of a multi-axis force sensor and a controller for measuring the forces (x-direction force, y-direction force and z-direction force) and sending the measured forces to the robot's controller (PLC: Programmable Logic Controller). In this paper, the force measurement and communication system was designed and fabricated by using a DSP (Digital Signal Processor). An environment test and a grinding and deburring test using an industrial robot with the force measurement and communication system with three-axis force sensor were carried out to characterize the system. The tests showed that the system could safely measure the forces from the three-axis force sensor and send the measured forces to the industrial robot's controller while the grinding and deburring test was performed. Thus, it is thought that the fabricated force measurement and communication system could be used for controlling the force for an industrial robot's grinding and deburring.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.468-472
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• 2004

In this paper a VLSI design for the automatic magnetizing system has been presented. This is the design of a peripheral controller, which magnetizes CRTs and computers monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a O.8um CMOS SOG(Sea of Gate) technology of ETRI. Most of the PPI functions has been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "apos;Linear delay predict model"apos; was suggested in the LODECAP(LOgic Design Capture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new "apos;delay predict equationapos;" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.3
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• pp.43-48
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• 2000

In this paper, CPLD(Complex Programmable Logic Device) controller designed with VHDL is developed. With the controller, the harmonics from 3 phase diode rectifier are suppressed and power factor is also improved. The input current of diode rectifier is drawn from the ac mains only during the period in the ac cycle when the instantaneous voltage is greater than the voltage across the dc-link capacitor. The three bidirectional switches rated at very small power are installed in a conventional three phase diode rectifier. Using CPLD controller, an idle current charges to capacitors continuously. Results of simulation and experimental demonstrate a reduction of harmonics, a improvement of power factor and THD.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.1-17
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• 2016

The separated management and operation of commercial IP/optical multilayer networks makes network operators look for a unified control plane (UCP) to reduce their capital and operational expenditure. Software-defined networking (SDN) provides a central control plane with a programmable mechanism, regarded as a promising UCP for future optical networks. The general control and scheduling mechanism in SDN-based optical burst switching (OBS) networks is insufficient so the controller has to process a large number of messages per second, resulting in low network resource utilization. In view of this, this paper presents the burst-flow scheduling mechanism (BFSM) with a proposed scheduling algorithm considering channel usage. The simulation results show that, compared with the general control and scheduling mechanism, BFSM provides higher resource utilization and controller performance for the SDN-based OBS network in terms of burst loss rate, the number of messages to which the controller responds, and the average latency of the controller to process a message.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.10a
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• pp.292-297
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• 2004

The conventional computerized numerical controller (CNC) of machine tools has been increasingly replaced by a PC-based open architecture CNC (OAC) which is independent of the CNC vendor. The OAC and machine tools with OAC led the convenient environment where it is possible to implement user-defined application programs efficiently within CNC. Tis paper proposes a method of operational fault cause diagnosis which is based on the status of programmable logic controller (PLC) in machine tools with OAC. The operational fault is defined as a disability state occurring during normal operation of machine tools. The faults are occupied by over 70% of all faults and are also unpredictable as most of them occur without any warning. Two diagnosis models, the switching function (SF) and the step switching function (SSF), are propose in order to diagnose the fault cause quickly and exactly. The cause of an occurring fault is logically diagnosed through a fault diagnosis system (FDS) using the diagnosis models. A suitable interface environment between CNC and develope application modules is constructed in order to implement the diagnostic functions in the CNC domain. The diagnosed results were displayed on a CNC monitor for machine operators and provided to a remote site through a web browser. The result of his research could be a model of the fault cause diagnosis and the remote monitoring for machine tools with OAC.