• KIISE Transactions on Computing Practices
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• v.23 no.2
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• pp.97-103
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• 2017

Many hardware-based regular expression matching architectures have been proposed for high-performance matching. In particular, regular expression processors, which perform pattern matching by treating the regular expressions as the instruction sequence like general purpose processors, have been proposed. After instruction sequence and data are provided in the instruction memory and data memory, respectively, a regular expression processor can perform pattern matching. To use a regular expression processor as a coprocessor, we need the host interface to transfer the instruction and data into the memory of a regular expression processor. In this paper, we design and implement the host interface between a host and a regular expression processor in the DE1-SoC board and the application program interface. We verify the operations of the host interface and a regular expression processor by executing the application programs which perform pattern matching using the application program interface.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Transactions of the Korean Society of Automotive Engineers
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• v.8 no.3
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• pp.190-197
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• 2000

A graphic vehicle modeling pre-processing program and a visualization post-processing program have been developed for AutoDyn7, which is a special program for vehicle dynamics. The Rapid-App for GUI(Graphic User Interface) builder and the Open Inventor for 3D graphic library have been employed to develop these programs in Silicon Graphics workstation. A Graphic User Interface program integrates vehicle modeling pre-processor, AutoDyn7 analysis processor, and visualization post-processor. In vehicle modeling pre-processor, vehicle hard point data for a suspension model are automatically converted into multibody vehicle system data. An interactive graphics capabilities provides suspension modeling aides to verify user input data interactively. In visualization post-processor, vehicle virtual test simulation results are animated with virtual testing environments.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.359-362
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• 2002

In this paper, we propose a structure of 800bps high speed router and a gigabit Ethernet line interface board. Having Programmability, network processor is applied to gjgabit Ethernet line interface board. Also, we propose a new method to upgrade image files that consist of operating system and drivers. It is possible to upgrade image files for several boards at once and to reduce the elapsed time for image upgrade using tile proposed method.

• Journal of Internet Computing and Services
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• v.21 no.1
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• pp.103-110
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• 2020

The EDISON is a platform that supports numerical analysis for problem solving in computational science and engineering. We provide a cloud service for users, and provide an environment to access and execution of the simulation service on the web. For now, the EDISON platform provides simulation services for eight applied field on computational science engineering. Users can check the numerical analysis result by web in the computational science and engineering platform. In addition, various services such as community activity with other researchers, and the configuration of simulation environment by user 's needs can be provided. A representative service of the EDISON platform is a web-based simulation service that performs numerical analysis for problem solving of various computational science and engineering. Currently, EDISON platform provides workbench simulation service. It is the web-based simulation execution environment, and result analysis to provide simulation regardless of various personal computing resource or environment in each numerical analysis. In this paper, we build an interface for pre and post processor that can be used in conjunction with the workbench-based simulation service provided by EDISON platform. We provide a development environment with interface that is implemented by applying a pre and post processor optimized for the simulation service. According to simulation and execution are performed by linking the new workbench-based simulation service to the pre and post processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1162-1169
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• 2012

One of the important operational requirements for mission critical Ethernet networked system is having the fault tolerant capability. Such capability can be obtained by equipping multiport Network Interface Card (NIC) in each node in the system. Conventional NIC uses two or more Media Access Controls (MACs) and a co-processor for the MAC switching whenever an active port fails. Since firmware is needed for the co-processor, longer fail-over switching and degraded throughput can be generally expected. Furthermore the system upgrading requiring the firmware revision in each tactical node demands high cost. In this paper we propose a novel single MAC based NIC that does not use a co-processor, but just use general discrete building blocks such as MAC chip and switching chip, which results in better performances than conventional method. Experimental results validate our scheme.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.295-297
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• 2002

최근 들어, 냉장고, 세탁기, TV 등과 같은 가정내의 가전들을 효과적으로 제어하고, 웹에서의 접근을 위한 홈 네트워크 기술에 많은 관심이 모아지고 있다. 홈 네트워크는 가전, 센서, 스위치, 제어기등과 링크할 수 있으며 멀티미디어 데이터의 전달을 위한 인프라의 제공 및 애플리케이션에 대한 사용자 인터페이스를 제공한다. 이러한 다양한 멀티미디어 데이터를 효과적으로 처리하기 위해서는 홈 게이트웨이가 필요하며, 이러한 홈 게이트웨이에 대한 연구가 활발하게 진행되고 있다. 그러나 다양한 데이터 구조의 처리를 위해 IEEE1394, Bluetooth, LonWorks, WLAN, HomePNA, PLC 둥과 같은 다양한 기술의 사용으로 인해 현재 홈게이트웨이는 매우 복잡한 구조를 가지게 되며, 기기간 상호 운용성도 보장하기 어려운 실정이다. 이에 본 논문에서는 홈 네트웍에서 존재하는 다양한 미디어 데이터를 효과적으로 처리할 수 있는 새로운 홈게이트웨이의 구조를 설계하고, 각각의 미디어 데이터를 인터워킹 가능한 패킷으로 만들어 주는 Media Processor와 서로 다른 미디어간의 인터워킹을 위한 Common Switch Interface의 구조에 대하여 기술한다.