• Journal of KIISE:Information Networking
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• v.33 no.2
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• pp.113-130
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• 2006

Recently with the explosive growth of Internet applications, the attacks of hackers on network are increasing rapidly and becoming more seriously. Thus information security is emerging as a critical factor in designing a network system and much attention is paid to Network Intrusion Detection System (NIDS), which detects hackers' attacks on network and handles them properly However, the performance of current intrusion detection system cannot catch the increasing rate of the Internet speed because most of the NIDSs are implemented by software. In this paper, we propose a new high performance network intrusion using Network Processor. To achieve fast packet processing and dynamic adaptation of intrusion patterns that are continuously added, a new high performance network intrusion detection system using Intel's network processor, IXP1200, is proposed. Unlike traditional intrusion detection engines, which have been implemented by either software or hardware so far, we design an optimized architecture and algorithms, exploiting the features of network processor. In addition, for more efficient detection engine scheduling, we proposed task allocation methods on multi-processing processors. Through implementation and performance evaluation, we show the proprieties of the proposed approach.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.5
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• pp.385-393
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• 2021

This study proposes a multi-core-based controller design for an ESC(Electronic Stability Control) system in an automotive multi-core processor. Considering the architectures of an automotive multi-core processor and an ESC system, the overall execution time has been optimized for multi-core platforms. The function module assignment, synchronization between cores, and memory assignment for core-dependent variables in automotive multi-core systems are evaluated. The ESC controller comprising five function modules is used herein. Based on the proposed design, the single-core controller is extended to multi-core controllers. Using multi-core optimization methods, such as function module assignment, semaphore, interrupt awakening, and variable assignment over cores, the ESC system is redesigned to a multi-core controller. Experimental results reveal that the execution time for the multi-core processor is reduced by 59.7% compared with that for the single-core processor.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.287-293
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• 2012

We introduce a methodology for the study of the application-level performance of time-sharing parallel jobs on a set of compute nodes in high performance clusters and report our findings. We assume that parallel jobs arriving at a cluster need to share a set of nodes with the jobs of other users, in that they must compete for processor time in a time-sharing manner and other limited resources such as memory and I/O in a space-sharing manner. Under the assumption, we developed a methodology to simulate job arrivals to a set of compute nodes, and gather and process performance data to calculate the percentage slowdown of parallel jobs. Our goal through this study is to identify a better combination of jobs that minimize performance degradations due to resource sharing and contention. Through our experiments, we found a couple of interesting behaviors for overlapped parallel jobs, which may be used to suggest alternative job allocation schemes aiming to reduce slowdowns that will inevitably result due to resource sharing on a high performance computing cluster. We suggest three job allocation strategies based on our empirical results and propose further studies of the results using a supercomputing facility at the San Diego Supercomputing Center.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.334-336
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• 2002

본 논문에서는 스타그래프 다중처리시스템을 위한 새로운 프로세서 할당방범을 제안한다. 기존의 할당방법은 프로세서 단편화로 인해 작업을 처리할 서브스타를 형성하지 못하면 프로세서 할당이 지연되는 문제점이 있었다. 이러한 할당 지연은 작업의 대기시간을 증가시키고 시스템의 성능 향상을 제한한다. 본 논문에서 제안하는 할당방법은 프로세서 할당 지연이 발생하면 동적할당테이블을 사용하여 단편화된 프로세서의 주소론 재생성한다. 새로운 주소의 프로세서들로 가용 서브스타를 형성하여 할당함으로써 작업의 대기시간을 줄이고 프로세서 단편화를 최소화한다.

• International Journal of Advanced Culture Technology
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• v.9 no.4
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• pp.282-287
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• 2021

A multicore system must be able to take full advantage of the program's instruction and data parallelism. This study introduces the data replication technique as a support technique to maximize the program's instruction and data parallelism. Instruction level parallelism can be limited by data dependency. In this case, if data is replicated to each processor core and used, instruction level parallelism can be used to the maximum. The technique proposed in this study can maximize the performance improvement effect when applied to scientific applications such as matrix multiplication operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1549-1560
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• 2009

In the TDMA PON system, the DBA is essential for ONUs to send data efficiently to the upstream. In this paper, we implement a DBA processor for the G-PON OLT with downstream and upstream rate, 2.5 and 1.25 Gbps, respectively, The processor collects bandwidth request messages from ONUs at every cycle time and allocates properly bandwidth to each Alloc-ID with considering priority and fairness for traffics. In the proposed DBA algorithm, one cycle time consists of multiple G-PON frames ($m{\times}125{\mu}s$) for high link efficiency. In particular, the link efficiency is higher because the algorithm adopts a method that an additional overhead is eliminated when an allocated bandwidth is laid between two G-PON frames for an ONU. This enables that the processor flexibly allocates the bandwidth from zero to the maximum link capacity for an ONU. The proposed DBA processor is implemented with the FPGA and shows bandwidth allocating processes for ONUs with logic analyzer.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.1-6
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• 2017

Due to the recent advances in IoT technologies, reducing power consumption in battery-based IoT devices becomes an important issue. An IoT device is a kind of real-time systems, and processor voltage scaling is known to be effective in reducing power consumption. However, recent research has shown that power consumption in memory increases dramatically in such systems. This paper aims at combining processor voltage scaling and low-power NVRAM technologies to reduce power consumption further. Our main idea is that if a task is schedulable in a lower voltage mode of a processor, we can expect that the task will still be schedulable even on slow NVRAM memory. We incorporate the NVRAM memory allocation problem into processor voltage scaling, and evaluate the effectiveness of the combined approach.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.233-239
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• 2001

Among the operations in frequency domain for ADSL G.LITE Modem to perform, FFT and FEQ are most computation-intensive part, of which many researches have been focused on the efficient implementation. Previous papers suggested hardwares suitable for ADSL G.DMT system, which is not feasible for simple G.LITE system. The analysis of frequency domain operations and computational efficiency according to the allocation of hardware resources is performed in this paper. The suggested processor has the structure of one real multiplier and two real adders connected in parallel, which can perform the operations efficiently through the pipeline- and/or parallel-type job scheduling. The suggested processor uses less hardware resources than Kiss\`s ALU structure or FFT/IFFT processor suggested by Wang, so the suggested one is more suitable for G.LITE system than previous works.

• KIISE Transactions on Computing Practices
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• v.22 no.1
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• pp.1-7
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• 2016

When multiple applications are running concurrently on a multi-processor system, interferences between applications make it difficult to guarantee real-time constraints. We propose a novel interference analysis technique that allows sharing of share processors among dataflow applications, while satisfying real-time constraints. Based on the interference analysis, we develop a co-scheduling technique that aims to minimize the resource usage. Compared to an existent technique that involves converting application graphs to real-time tasks, the proposed technique shows better results in terms of resource usage, especially when it is applied to applications with tight time constraints.

• Journal of Korea Multimedia Society
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• v.20 no.9
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• pp.1559-1566
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• 2017

Recently in the IoT(Internet of Things) environment, a data collection in real-time through device's sensor has increased with an emergence of various devices. Collected data from IoT environment shows a large scale, non-uniform generation cycle and atypical. For this reason, the distributed processing technique is required to analyze the IoT sensor data. However if you do not consider the optimal scheduling for data and the processor of IoT in a distributed processing environment complexity increase the amount in assigning a task, the user is difficult to guarantee the QoS(Quality of Service) for the sensor data. In this paper, we propose APQTA(Adaptive Priority Queue-driven Task Allocation method for sensor data processing) to efficiently process the sensor data generated by the IoT environment. APQTA is to separate the data into job and by applying the priority allocation scheduling based on the deadline to ensure that guarantee the QoS at the same time increasing the efficiency of the data processing.