• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.92-95
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• 1991

Constant false alarm rate(CFAR) processors are useful for detecting radar targets in background for which all parameters in the statistical distribution are not known and may be nonstationary. The well known "cell averging" (CA) CFAR processor is known to yield best performance in homogeneous case, but exhibits severe performance in the presence of an interfering target in the reference window or/and in the region of clutter edges. The "order statistics"(OS) CFAR processor is known to have a good performance above two nonhomogeneous cases. The modified OS-CFAR processor, known as "trimmed mean"(TM) CFAR processor performs somewhat better than the OS-CFAR processor by judiciously trimming the ordered samples. This paper proposes and analyzes the performance of a new CFAR processor called the "maximum trimmed mean"(MX-TM) CFAR processor combining the "greatest of"(GO) CFAR and TM-CFAR processors. The MAX operation is included to control false alarms at clutter edges. Our analyses show that the proposed CFAR processor has similar performance TM- and OS-CFAR processors in homogeneous case and in the precence of interfering targets, but can control the false rate in clutter edges. Simulation results are presented to demonstrate the qualitative effects of various CFAR processors in nonhomogeneous clutter environments.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.917-920
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• 2005

This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.3
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• pp.185-191
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• 2002

A window-based multibody dynamics program CADyna(Computer Aided Dynamics) is developed and applied for kinematic and dynamic analysis ova steering system. The program is composed oft pre-processor, a main processor, and a post-processor. The pre-processor is developed with Visual C7+ and the post-processor is developed with OpenGL and TeeChart. The main processor generates the equations of motion employing velocity transformation technique. The developed program is customized for the design of an intermediate shaft in a steering system.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.1 s.94
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• pp.61-67
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• 1999

A laser Doppler vibrometer based on the laser heterodyne interferometry is employed to measure the vibration velocity of vibrating objects. In this paper, we propose a real time analog signal processor of a laser Doppler vibrometer to reduce the degradation of Doppler signals mainly caused by environmental noises. In the proposed real time signal processor of an laser Doppler vibrometer, a pre-processor and a logical motion direction detector are designed to reduce the detection errors of the object motion direction. Also, a noise detection and rejection circuit is designed to reject the unfiltered noises.

• Magazine of the Korean Society of Agricultural Engineers
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• v.39 no.2
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• pp.103-112
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• 1997

A CELTHYM(CEll-based Long-term HYdrologic Model), a pre-processor and a post-processor that can he integrated with geographic information system(GIS) were developed to predict the stream flow of a small agricultural watershed. Three kinds of routines, that are watershed boundary extraction routine(WBER), curve number calculation routine(CNR) and maximum available soil moisture calculation routine(MASR) composed pre-processor that was nicely interfaced with CELTRYM and GIS. Two kinds of routines, grapher and map composer composed post-processor that was well adapted CELTHYM output to chart making and GIS map making. The developed pre-post processor was useful for the GIS integration and spatial comprehension of the CELTHYM output.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].