• Title/Summary/Keyword: process fault

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A Study on the Fault Diagnosis of Roller-Shape Using Frequency Analysis of Tension Signals and Artificial Neural Networks Based Approach in a Web Transport System

  • Tahk, Kyung-Mo;Shin, Kee-Hyun
    • Journal of Mechanical Science and Technology
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    • v.16 no.12
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    • pp.1604-1612
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    • 2002
  • Rollers in the continuous process systems are ones of key components that determine the quality of web products. The condition of rollers (e.g. eccentricity, runout) should be consistently monitored in order to maintain the process conditions (e.g. tension, edge position) within a required specification. In this paper, a new diagnosis algorithm is suggested to detect the defective rollers based on the frequency analysis of web tension signals. The kernel of this technique is to use the characteristic features (RMS, Peak value, Power spectral density) of tension signals which allow the identification of the faulty rollers and the diagnosis of the degree of fault in the rollers. The characteristic features could be used to train an artificial neural network which could classify roller conditions into three groups (normal, warning, and faulty conditions) The simulation and experimental results showed that the suggested diagnosis algorithm can be successfully used to identify the defective rollers as well as to diagnose the degree of the defect of those rollers.

A Grid Service based on OGSA for Process Fault Detection (프로세스 결함 검출을 위한 OGSA 기반 그리드 서비스의 설계 및 구현)

  • Kang, Yun-Hee
    • Proceedings of the Korea Contents Association Conference
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    • 2004.11a
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    • pp.314-317
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    • 2004
  • With the advance of network and software infrastructure, Grid-computing technology on a cluster of heterogeneous computing resources becomes pervasive. Grid computing is required a coordinated use of an assembly of distributed computers, which are linked by WAN. As the number of grid system components increases, the probability of failure in the grid computing is higher than that in a traditional parallel computing. To provide the robustness of grid applications, fault detection is critical and is essential elements in design and implementation. In this paper, a OGSA based process fault-detection services presented to provide high reliability under low network traffic environment.

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A Fault-Tolerance Agent for Multimedia Collaboration Works running on Vehicle Environment (차량 환경 상에서 멀티미디어 공동 작업을 위한 결함 허용 에이전트)

  • Ko, Eung-Nam
    • Journal of Advanced Navigation Technology
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    • v.15 no.1
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    • pp.157-161
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    • 2011
  • This paper explains an error process for multimedia collaboration works with session management running on vehicle network environment. This system consists of an FDA and FRA. FDA is an agent that detects an error by hooking techniques for multimedia system based on vehicle network environment with session management. FRA is a system that is suitable for recovering software error for multimedia system with session management based on vehicle network environment. This paper describes only FRA. When multiple local sessions is opened, each local session manager sends information of participant to global session manager and take current information about session of processing in network.

A study on $YBa_2Cu_3O_x$ thick films by diffusion process for a superconducting fault current limiter (확산법을 이용한 사고전류제한기용 $YBa_2Cu_3O_x$ 후막연구)

  • Cho, Dong-Eon;Yim, Seong-Woo;Choi, Myung-Ho;Han, Byoung-Sung
    • Proceedings of the KIEE Conference
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    • 1998.07d
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    • pp.1516-1518
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    • 1998
  • $YBa_2Cu_3O_x$(Yl23) Superconducting thick films on $Y_2BaCuO_5$(Y211) substrate were Prepared by surface diffusion process between $BaCuO_2$+CuO composite coating powder and a Y2ll substrate. X-ray diffraction shows that the Yl23 layer onto Y2ll substrate is the orthorhombic crystal structure. The specimen heated at $940^{\circ}C$ for 2h showed the maximum $J_c$ fo 500A/$cm^2$. Based on optimal condition, the superconducting fault current limiter(FCL) having a current limiting area 1mm wide and 66mm long was fabricated on Y211 substrate. A typical current limiting waveform was measured. When a voltage of 3V was applied, the fault current with a peak of 15A was limited to about 0.11A.

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A Study on Characterization of Thick Film used as Superconducting Fault Current Limiter (고온 초전도 전류제한기용 후막의 특성 연구)

  • 조동언;박경국;김동원;정길도;한병성
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.12
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    • pp.1139-1145
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    • 1998
  • In this paper, to fabricate a superconducting fault current limiter(FCL) of thick film type, $YBa_2Cu_3O_X superconducting thick films were fabricated by surface diffusion process using the screen printing method. Powder mixture of $3BaCuO_2$+2CuO was screen printed on $Y_2BaCuO_5$(d=15mm). And critical current densities of the thick films were observed as the sintering temperature(92$0^{\circ}C$~95$0^{\circ}C$) and holding time(2h~10h). Based on experimental data, the thick films for superconducting FCL were sintered at $940^{\circ}C$ in 2 hours. The superconducting FCL with a current limiting area of 1mm wide and 66mm long was prepared on $Y_2BaCuO_5$ substrate. To measure the characterization of the fabricated FCL, an alternating voltage (60Hz) was applied to the FCL in 77K liquid nitrogen. At an applied voltage of 4V, the FCL was limited from 20A into 0.6A not farther than 0.5ms.

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Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits (혼합형 조합 회로용 고장 시뮬레이션 시스템의 설계 및 구현)

  • Park, Yeong-Ho;Son, Jin-U;Park, Eun-Se
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.1
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    • pp.311-323
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    • 1997
  • This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

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An Improved Dual-mode Laser Probing System for Fault Injecton Attack (오류주입공격에 대한 개선된 이중모드 레이저 프로빙 시스템)

  • Lee, Young Sil;Non, Thiranant;Lee, HoonJae
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.24 no.3
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    • pp.453-460
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    • 2014
  • Fault injection attack is the process of attempting to acquire the information on-chip through inject artificially generated error code into the cryptographic algorithms operation (or perform) which is implemented in hardware or software. From the details above, the laser-assisted failure injection attacks have been proven particularly successful. In this paper, we propose an improved laser probing system for fault injection attack which is called the Dual-Laser FA tool set, a hybrid approach of the Flash-pumping laser and fiber laser. The main concept of the idea is to improve the laser probe through utilizing existing equipment. The proposed laser probe can be divided into two parts, which are Laser-I for laser cutting, and Laser-II for fault injection. We study the advantages of existing equipment, and consider the significant parameters such as energy, repetition rate, wavelength, etc. In this approach, it solves the high energy problem caused by flash-pumping laser in higher repetition frequency from the fiber laser.

Timely Sensor Fault Detection Scheme based on Deep Learning (딥 러닝 기반 실시간 센서 고장 검출 기법)

  • Yang, Jae-Wan;Lee, Young-Doo;Koo, In-Soo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.1
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    • pp.163-169
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    • 2020
  • Recently, research on automation and unmanned operation of machines in the industrial field has been conducted with the advent of AI, Big data, and the IoT, which are the core technologies of the Fourth Industrial Revolution. The machines for these automation processes are controlled based on the data collected from the sensors attached to them, and further, the processes are managed. Conventionally, the abnormalities of sensors are periodically checked and managed. However, due to various environmental factors and situations in the industrial field, there are cases where the inspection due to the failure is not missed or failures are not detected to prevent damage due to sensor failure. In addition, even if a failure occurs, it is not immediately detected, which worsens the process loss. Therefore, in order to prevent damage caused by such a sudden sensor failure, it is necessary to identify the failure of the sensor in an embedded system in real-time and to diagnose the failure and determine the type for a quick response. In this paper, a deep neural network-based fault diagnosis system is designed and implemented using Raspberry Pi to classify typical sensor fault types such as erratic fault, hard-over fault, spike fault, and stuck fault. In order to diagnose sensor failure, the network is constructed using Google's proposed Inverted residual block structure of MobilieNetV2. The proposed scheme reduces memory usage and improves the performance of the conventional CNN technique to classify sensor faults.

Circuit partitioning to enhance the fault coverage for combinational logic (조합논리회로의 고장 검출율 개선을 위한 회로분할기법)

  • 노정호;김상진;이창희;윤태진;안광선
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.4
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    • pp.1-10
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    • 1998
  • Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

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A study on the control system with dual structure to enhance its reliability (제어 시스템의 신뢰도 향상을 위한 이중화 구조 연구)

  • 박세화;문봉채;김병국;변증남
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10a
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    • pp.773-778
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    • 1990
  • In this paper, a reliable control system structured with dual CPU modules and dual I/O modules is implemented as a means of achieving a highly reliable fault tolerant control system. For this, faults in the system modules are first examined, and a fault detection technique consisting of self diagnostic, comparison process, and exception processing is applied. Also reliability analysis is conducted for the discrete time Markov model with dual structure. It is shown quantitatively that the reliability is improved in the control system with dual structure in comparison with a system with single module structure.

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