• 전자공학회논문지C
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• 제34C권6호
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• pp.11-21
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• 1997

The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.

• 한국정보기술응용학회:학술대회논문집
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• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• 국제학술발표논문집
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• The 9th International Conference on Construction Engineering and Project Management
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• pp.213-221
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• 2022

Defects are the risk factors in the construction process of buildings. They cause damage, delaying the construction duration. They especially cause adverse effects on the top-down construction method. This study analyzed the degree of construction delay induced by each work type, focusing on defects in the top-down method. Then, we derived construction delay induction coefficient from different work types in order by using the severity of construction delay per defect and the occurrence probability of defect; this assessment model measures the impact of defects on construction delay for each work type. Furthermore, by comparing each work type based on the defect frequency and the construction delay induction coefficient, we found work types that need to be administered attentively. We identified that plastering work was easy to overlook, requiring caution in defect management. This study provides an efficient defect management system suitable for the buildings that are built using the top-down construction method.

• 한국건설관리학회:학술대회논문집
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• 한국건설관리학회 2007년도 정기학술발표대회 논문집
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• pp.637-642
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• 2007

건설공사 한 프로젝트의 전체공기는 개별 작업들이 수행된 날짜의 합이라 할 수 있다. 개별 작업들에서 지연이 발생할 경우 전체 공기 또한 늦어지기 마련이다. 이러한 개별 작업의 계획상에서 작업이 수행될 확률을 높인다면 프로젝트의 공기달성 확률 또한 높아지게 될 것이다. 따라서, 계획상의 작업 실행여부 확인을 위하여 건설 생산프로세스에서 각 작업의 수행을 저해하는 제약요인을 도출하여 작업여건분석을 한다. 작업여건분석을 통해 저해요인 사전 제거와 작업간의 상호의존성을 파악으로 작성된 개별 작업계획들의 실행 가능성 확임함으로써 공사전체의 공기지연을 방지하는 체계를 구축하고자 한다.

• 전기전자학회논문지
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• 제27권3호
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• pp.234-238
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• 2023

본 논문에서는 PVT(process, voltage, and temperature) 변화에 대한 보상기능을 가지는 시간-디지털 변환기(time-to-digital converter : TDC)를 제안한다. 일반적인 지연 라인(delay line) 기반의 TDC는 인버터의 전파 지연을 기반으로 시간을 측정하기 때문에 근본적으로 PVT 변화에 민감하다. 이 논문은 PVT 변화에 의한 전파 지연을 보상하여 TDC의 해상도 변화를 최소화시키는 방법을 제안한다. 또한 넓은 입력 측정 범위(detection range)를 갖기 위해 Cyclic Vernier TDC (CVTDC) 구조를 채택한다. 제안하는 PVT보상 기능의 CVTDC는 45nm CMOS 공정으로 설계되어, 8mW의 전력을 소모하며, 5 ps의 TDC 해상도 및 약 5.1 ns 입력 측정 범위를 갖는다.

• 한국측량학회지
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• 제33권2호
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• pp.123-129
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• 2015

알고리즘의 유연성 및 효율성으로 인해 GPS 이동측위 시 칼만필터가 주로 사용되어 왔으며 동시에 다양한 계통오차의 제거가 가능한 상대측위 기법이 널리 사용되어 왔다. 하지만 기선의 길이가 길어지게 되면 상대측위 기법을 사용하더라도 대기효과를 충분히 제거하기 어렵기 때문에 이 경우 제거되지 않고 남아 있는 대기효과를 상태벡터에 추가하여 추정을 하기도 한다. 칼만필터를 이용하는 경우 일반적으로 대기효과는 랜덤워크 혹은 일차가우스-마르코프 프로세스로 모델링하게 되는데 이때 프로세스 잡음에 대한 정확한 모델링이 필수적이다. 본 연구에서는 대기효과에 해당되는 프로세스 잡음 모델링을 위해 필요한 매개변수를 결정하였다. 이를 위해 이중차분 전리층 지연값과 천정방향 습윤지연값을 이용하여 실험적 자기상관함수를 계산하였으며 이를 통해 프로세스 잡음 모델링에 필요한 매개변수를 계산하였다. 결정된 매개변수값들은 유사한 대기환경에서 취득된 데이터에 대한 프로세스 잡음 모델링 시 직접 사용될 수 있으며 유사한 대기환경이 아닌 경우일 지라도 초기 근사값으로 활용될 수 있을 것이다.

• 한국의류학회지
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• 제37권4호
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• pp.526-539
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• 2013

This study analyzed the effects of internet fashion consumer's anticipated regret and the selection difficulty on decision making delay and purchase switching intention. The survey was conducted in 2012 on internet fashion consumers in their 20s to 40s from May 1 to June 30; subsequently, 487 responses were used for the data analysis. The anticipated regret of internet fashion consumers was composed of product, service, social psychology, and function-related anticipated regret. The selection difficulty of internet fashion consumers was composed of process, information, and experience-related selection difficulty. There are significant differences in anticipated regret, selection difficulty, decision making delay, and purchase switching intention by gender. The anticipated regret (product, service, and social psychology-related anticipated regret) and selection difficulty effected decision making delay. In addition, the anticipated regret for product and selection difficulty by process or information influenced purchase switching intention. The results of this study provide useful information on the success and efficient operation of internet shopping malls.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• 한국건축시공학회지
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• 제12권6호
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• pp.636-647
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• 2012

Construction projects have become so large, complicated and incredibly high-tech that process management is currently considered one of the most important issues. Unlike typical manufacturing industries, most major construction activities are performed in the open air and thus are exposed to various environmental factors. Many studies have been conducted with the goal of establishing efficient techniques and tools for overcoming these limitations. Productivity analysis and prediction, one of the related research subjects, must be considered when evaluating approaches to reducing construction duration and costs. The aim of this research is to present a quantified impact analysis of construction delay factors on construction productivity of a steel staircase system, which has been widely applied to high rise building construction. It is also expected to improve the process by managing the factors, ultimately achieving an improvement in construction productivity. To achieve the research objectives, this paper analyzed different delay factors affecting construction duration by means of multiple regression analysis focusing on steel staircase systems, which have critical effects on the preceding and subsequent processes in structure construction. Statistical analysis on the multiple linear regression model indicated that the environment, labor and material delay factors were statistically significant, with 0.293, 0.491, and 0.203 as the respective quantified impacts on productivity.

• 전기학회논문지
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• 제56권6호
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.