• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.14-21
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• 1997

In delay-optimized designs, timing failures due to manufacturing delay defects are more likely to occur because the average timing slacks of paths decrease and the system becomes more sensitive to smaller delay defect sizes. In this paper, the impact of delay optimized logic circuits on delay fault testing will be discussed and compared to the case for non-optimized designs. First, we provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Next we also discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults. Finally, we will give some recommendations on the determination of the system clock time so that the delay-optimized design will have the same manufacturing yield as the non-optimized design and on the determination of delay fault coverage in the delay-optimized design in order to have the same defect-level for delay faults as the non-optimized design, while the system clock time is the same for both designs.

• Journal of Biomedical Engineering Research
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• v.9 no.1
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• pp.87-92
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• 1988

In this paper, a new focusing method, to be called the pipelined sampled delay focusing (PSDF), is implemented. This method improves the lateral resolution in ultrasound imaging system. In PSDF, the analog belay lines are no longer necessary because sampling sum process can replace the conventional delay sum process. Also, the method offers continuous dynamic focusing on the resolution pixel basis, and eliminates the constraint that the maximum delay time is less than the sampling interval. Second order sampling is adopted in order to extend the sampling interval.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.300-305
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• 2004

In this paper, new design equations based on the pole-zero analysis for multi-layered interdigital stripline linear group delay bandpass filter with tap input ports are presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of $\pm$0.1nS for LTCC technology or multilayered PCB technology is designed. In the design process, it is not necessary to simulate the entire structure, as the simulation of half structures is sufficient. Good results can be attained after the optimizing process was performed three times using the proposed equations and a commercial EM simulator.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.12
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• pp.4389-4410
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• 2014

Network coding is a promising technology that increases system throughput by reducing the number of packet transmissions from the source node to the destination node in a saturated traffic scenario. Nevertheless, some packets can suffer from end-to-end delay, because of a queuing delay in an intermediate node waiting for other packets to be encoded with exclusive or (XOR). In this paper, we analyze the delay according to packet arrival rate and propose two network coding schemes, iXOR (Intelligent XOR) and oXOR (Optimal XOR) with Markov Decision Process (MDP). They reduce the average delay, even under an unsaturated traffic load, through the Holding-${\chi}$ strategy. In particular, we are interested in the unsaturated network scenario. The unsaturated network is more practical because, in a real wireless network, nodes do not always have packets waiting to be sent. Through analysis and extensive simulations, we show that iXOR and oXOR are better than the Distributed Coordination Function (DCF) without XOR (the general forwarding scheme) and XOR with DCF with respect to average delay as well as delivery ratio.

• Journal of the Korea Institute of Building Construction
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• v.9 no.1
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• pp.89-94
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• 2009

A study was performed the analysis for the schedule delay of the public housing. To perform this study, the first study existing research literature on the cause of the schedule delay was considered. The based on existing study, this study selected the cause of schedule delay. For check of the schedule delay, this study was compared the monthly schedule and the work diary. Survey was conducted for using the selected cause of schedule delay. And the importance was calculated for using the AHP method. In a case site, the cause of the schedule delay was analyzed. The last, the delay cause was presented the map of cause of effect the based on the delay cause of a case site.

• The Journal of the Acoustical Society of Korea
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• v.22 no.8
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• pp.680-686
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• 2003

Digital waveguide model is a general method that is used in physical modeling of musical instruments. Wave motion is analyzed by time or by space in digital waveguide model. Because sampling is made via time, it is general that musical instrument model is described by wave motion of time. In this paper, we synthesized the musical instrument sound by adding instrument body model to the spatial based string model. In this way, we could improve sound quality and process musical instrument model's tone control variables effectively. We explained about delay error that happens in string and body in space based sampling and showed method to process fractional delay using FD (Fractional Delay)filter. Finally, we explained the relation between tone quality and number of delays. And we also compared the result with time base digital waveguide model.

• Journal of the Korean Society of Systems Engineering
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• v.11 no.1
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• pp.9-24
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• 2015

Construction industry faces a lot of inherent uncertainties and issues and the construction phase of nuclear power project is not free from this risk. This paper investigates promising methodologies to be used on nuclear power plant (NPP) construction schedule delay risk assessment by using entry level systems engineering approach. This study contains how the initial concept for the risk assessment methodology has been developed. In this point of view, this work structured on three main phases: needs analysis (NA), concept exploration (CE), and concept definition (CD) through systems engineering (SE) approach. Traditionally, the SE process is applied to technical development programs but this study opens up a new avenue that SE can also be successfully applied to the development and optimization of the risk assessment model. This study provides a rational and systematic process for developing and selecting the best risk assessment model. This paper selects analytic hierarchy process (AHP) method to assess NPP construction schedule delay risk for international project. As conclusion, the proposed concept and selected method can discriminate successfully and clearly among schedule delay risk assessment methods.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.723-726
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• 1998

Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.