• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• Journal of the Korea Institute of Building Construction
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• v.21 no.4
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• pp.347-359
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• 2021

Recently, construction projects have emerged in the form of program management, which is complicated by the large-scale of construction, and requires astronomical construction costs. In particular, projects that absolutely require management at the program level, such as large-scale construction projects, require overall control of the planned schedule and cost as a set of various projects, including infrastructure. But in Korea, there is no specific management standard for delays in construction. In order to avoid the risk of cost increase and project delay in the program-level construction project, it is necessary to apply more systematic management standards to prevent delay and to take a more preemptive response in the construction process. Therefore, in this study, a delay management index (DMI) was developed to successfully carry out large-scale construction projects at the program level and prevent delays in advance. In addition, case studies were conducted for large-scale construction projects, and a delay prevention system was established for program-level construction projects.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1868-1879
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• 1996

There are limitations to process high bandwidth traffic in B-ISDN with mesh- topology single bus architecture of current mobile communication system. And, it is impossible to import ATM switch using fixed length packet rather than variable length packet. Some implementations are able to process variable length packet, but there are some problems such as pre-processing for synchronization and bit delay. In this paper, we design a concentrator that can manipulate variable length packet without additional pre-process. There is on bit delay for packet starting signal in input interface, So it is more efficient to process packets, such that the concentrator can reduce he processing time as $\ulcornerlog2N\lrcorne＋1$ bit-time rather than N bit-time delay in ordinary concentrator. It is expected that the mobile communication system with partial mesh topology bus adopting the knockout switch architecture can process high bandwidth traffic in B-ISDN.

• Korean Journal of Construction Engineering and Management
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• v.6 no.3 s.25
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• pp.81-89
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• 2005

Delay schedule coming about duration extension is happening essentially because public construction project consist of many sub contractor. The method which can calculate delay day is suggested by many studies in case of happing delay schedule, but It is difficult to apply to real construction project because there is no mention about the control of The law of contract according to delay schedule. The law of Contract which is cost of account has more uncertain problem than FIDIC condition of contract. This study suggests method which can make extension of duration procedure clear in case of happing the reason of design change related with activity duration during carrying on construction, and a submission process of the reason of duration extension and modify schedule making way about section which is basis of calculating contract amount clear.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.17 no.1
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• pp.130-137
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• 2018

In long freight trains, there is a brake time delay in the neighboring freight cars that causes damage and fractures of couplers, especially the knuckle of them. If there is a problem for couplers in the cars, this could cause a derailment and lead to damage of human life and property damage. In this study, maximum forces on the couplers are studied when a long freight car brakes, with brake delay time and coupler gap. We have made a dynamic model of 50 freight cars and couplers, applying contact between couplers and a characteristic curve for expressing force and displacement of buffers with SIMPACK, a multi-body dynamics program. We use EN 14531-2 from the British Standards Institution, a standard of freight car brakes for the verification of the dynamic model. We also use a simplified method to analyze the dynamic model of 50 freight cars. With changing coupler gap and brake delay time, we do comparative analysis with AAR M-201 from the Association of American Railroads, a standard of AAR couplers. From this result, we find that the standard on fatigue limit is satisfied, such that the brake delay time is within 0.06 second if the coupler gap of the AAR coupler is within 20 millimeters.

• Journal of Drive and Control
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• v.15 no.3
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• pp.21-28
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• 2018

We propose a tension controller based on a time-delay estimation (TDE) technique for a winding machine. Firstly, we perform the necessary calculations to derive a mathematical model of the winding machine. In this sense, it is revealed that the roll radius of the winding machine is characteristically seen to be increasing or decreasing during the winding process. That being said, it is noted that the parameters of the winding machine are coupled and constantly changing during this process. Understandably then, it is noted that the model is shown to be nonlinear and time-varying. Secondly, we propose the way to apply the TDE based controller which is the so-called Time-delay Control (TDC). The TDC utilizes the time-delayed information intentionally to compensate the nonlinear and time-varying characteristics. As we have seen, the proposed controller consists of two parts: one is a TDE component, and the other is an error dynamics component which is defined by a user. In a computer simulation based on the Matlab/Simulink program, the proposed controller is compared with a conventional PID controller, which is widely used in the tension control of the winding machine. The proposed controller reduces the incidence of overshoot and steady-state error in the tension control, as compared to the conventional PID controller.

• Korean Journal of Construction Engineering and Management
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• v.8 no.3
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• pp.125-133
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• 2007

If project time extension were required in the construction projects, either liquidated damages or extension costs should be applied according to causation of the schedule delays. However, in actual cases it is not applied so far according to the contract conditions. The reason why this situation happened Is that function of the present planning and scheduling is not working feasibly. The CPM schedule could not provide a proper solution for apportioning responsibility for the schedule delays. This situation could be considered as breach of contract and will cause potential disputes for schedule delay. Therefore, in this research process based contract administration model for construction delay claim is proposed to prevent schedule delay and solve the claims. The model is based on pro-active management for causation of delay to provide apportionment of responsibility and written evidences.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.